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/llvm-project/lldb/source/Plugins/Trace/intel-pt/
H A DLibiptDecoder.cpp32 auto InsnDecoderDeleter = [](pt_insn_decoder *decoder) { in __anonc6608bc50102() argument
33 pt_insn_free_decoder(decoder); in __anonc6608bc50102()
36 auto QueryDecoderDeleter = [](pt_query_decoder *decoder) { in __anonc6608bc50202() argument
37 pt_qry_free_decoder(decoder); in __anonc6608bc50202()
86 static Error SetupMemoryImage(pt_insn_decoder *decoder, Process &process) { in SetupMemoryImage() argument
87 pt_image *image = pt_insn_get_image(decoder); in SetupMemoryImage()
136 PSBBlockAnomalyDetector(pt_insn_decoder &decoder, in PSBBlockAnomalyDetector() argument
139 : m_decoder(decoder), m_decoded_thread(decoded_thread) { in PSBBlockAnomalyDetector()
572 Expected<PSBBlockDecoder> decoder = PSBBlockDecoder::Create( in DecodeSingleTraceForThread() local
577 if (!decoder) in DecodeSingleTraceForThread()
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H A DTraceIntelPT.cpp212 for (auto &decoder : storage.thread_decoders) { in FindBeginningOfTimeNanos() local
213 Expected<std::optional<uint64_t>> tsc = decoder.second->FindLowestTSC(); in FindBeginningOfTimeNanos()
/llvm-project/llvm/test/TableGen/FixedLenDecoderEmitter/
H A DMultiOps.td30 // 1. Uses a complex operand without a decoder, and without named sub-ops.
31 // 2. Uses a complex operand with named sub-ops, but with a decoder as well.
33 …oderEmitter: operand "r1c" uses MIOperandInfo with multiple ops, but doesn't have a custom decoder!
/llvm-project/clang/test/Analysis/
H A Dsecurity-syntax-checks-nscoder.m30 void test(NSCoder *decoder) {
34 …[decoder decodeValueOfObjCType:"I" at:&x]; // available-warning{{Deprecated method '-decodeValueOf…
35 [decoder decodeValueOfObjCType:"I" at:&x size:sizeof(x)]; // no-warning
/llvm-project/llvm/test/TableGen/
H A DHwModeEncodeDecode2.td57 // ModeB decoder tables.
58 // In the suppressed case, this instruction appears in a single decoder table.
80 // In the default case, this instruction is duplicated into two Alt decoder
82 // In the suppressed case, this instruction appears in a single decoder table.
H A Dtrydecode-emission.td4 // have a complete decoder method that can determine if the bitpattern is valid
5 // or not then the decoder tries to find a more general instruction that
H A DVarLenDecoder.td37 (slice "$src.offset", 15, 0, (decoder "myCustomDecoder"))
43 (operand "$src.reg", 3, (decoder "myCustomDecoder"))),
/llvm-project/compiler-rt/lib/sanitizer_common/
H A Dsanitizer_stack_store.cpp219 SLeb128Decoder decoder(from, from_end); in UncompressDelta() local
221 for (; decoder != end; ++to, ++decoder) *to = *decoder; in UncompressDelta()
235 SLeb128Decoder decoder(from, from_end); in UncompressLzw() local
237 to = LzwDecode<uptr>(decoder, end, to); in UncompressLzw()
/llvm-project/llvm/test/DebugInfo/Generic/assignment-tracking/
H A Dremove-redundant-fwd-scan-linked.ll15 ;; 9 c decoder;
19 ;; 13 (&(&a)->decoder)->b = 0;
20 ;; 14 (&(&a)->decoder)->a = 0;
22 ;; 16 a.decoder.b = &d;
111 !20 = !DIDerivedType(tag: DW_TAG_member, name: "decoder", scope: !18, file: !3, line: 9, baseType: …
/llvm-project/llvm/test/CodeGen/SystemZ/
H A Dpostra-sched-expandedops.mir6 # instruction with 6 decoder slots.
17 # CHECK-NEXT: ++ Completed decode group: { SU(3):DL/FXa(4cyc)/LSU/6uops/GroupsAlone } (6 decoder sl…
18 # CHECK-NEXT: ++ | Current decoder group: <empty>
/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZSchedule.td11 // These resources are used to express decoder grouping rules. The number of
12 // decoder slots needed by an instructions is normally one, but there are
/llvm-project/clang/test/AST/
H A Dgen_ast_dump_json_test.py198 decoder = json.JSONDecoder(object_hook=OrderedDict)
204 (j, doc_start) = decoder.raw_decode(json_str[doc_start:])
/llvm-project/llvm/test/tools/llvm-mca/X86/
H A Duop-queue.s6 …4-unknown-unknown -mcpu=haswell -iterations=1500 -micro-op-queue-size=4 -decoder-throughput=2 -all…
10 …64-unknown-unknown -mcpu=btver2 -iterations=1500 -micro-op-queue-size=4 -decoder-throughput=1 -all…
/llvm-project/llvm/test/CodeGen/Mips/
H A Ddsp-spill-reload.ll10 ; object file encoder/decoder as the instruction mapping tables are used to
/llvm-project/lldb/test/API/tools/lldb-server/
H A DTestAppleSimulatorOSType.py23 except json.decoder.JSONDecodeError:
H A DTestLldbGdbServer.py1494 decoder = struct.Struct(format_str)
1495 decoded = decoder.unpack(content[: decoder.size])
/llvm-project/llvm/test/MC/Disassembler/ARC/
H A Dldst.txt117 # the different range of numbers helps exercise the S12 decoder.
/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrFormats.td167 (decoder "DecodeImm32"))
185 (decoder "DecodeImm32")),
H A DM68kInstrControl.td236 (decoder "DecodeImm32"))>;
268 (decoder "DecodeImm32"))>;
/llvm-project/llvm/include/llvm/Target/
H A DTarget.td553 // Is the instruction decoder method able to completely determine if the
556 // hasCompleteDecoder flag says whether the decoder method fully handles the
558 // If not then the decoder attempts to continue decoding when the decoder
564 // * InstB with bitpattern 0b000000?? but the associated decoder method
567 // The decoder tries to decode a bitpattern that matches both InstA and
571 // hasCompleteDecoder = 0 in InstB, the decoder is informed that
573 // valid or not. If DecodeInstB() returns Fail the decoder will attempt to
901 /// You can use `encoder` or `decoder` to specify a custom encoder or decoder
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/llvm-project/lldb/docs/use/
H A Dintel_pt.rst30 decoder library `LibIPT library <https://github.com/intel/libipt>`_.
/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrFormats.td41 // TableGen from using them for generation of the decoder tables.
/llvm-project/llvm/lib/Target/AVR/
H A DAVRInstrFormats.td172 // decoder method is needed.
/llvm-project/llvm/utils/TableGen/
H A DDecoderEmitter.cpp9 // It contains the tablegen backend that emits the decoder functions for
53 #define DEBUG_TYPE "decoder-emitter"
65 cl::desc("Suppress duplication of instrs into per-HwMode decoder tables"),
165 // Emit the decoder state machine table.
303 /// which could have been used by the decoder to resolve the conflict. The
304 /// decoder could try to decode the even/odd register numbering and assign to
305 /// VST4q8a or VST4q8b, but for the time being, the decoder chooses the "a"
792 // Emit the decoder state machine table.
1027 // The decoder function is just a big switch statement based on the
1028 // input decoder inde
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/llvm-project/llvm/test/MC/Disassembler/X86/
H A Dx86-64.txt460 # decoder tool provided by Intel, which we assume to be canonical even

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