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Searched refs:Val (Results 1 – 25 of 1291) sorted by relevance

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/llvm-project/llvm/include/llvm/ExecutionEngine/Orc/Shared/
H A DPerfSharedStructs.h95 static size_t size(const PerfJITRecordPrefix &Val) { in size() argument
97 static_cast<uint32_t>(Val.Id), Val.TotalSize); in size()
99 static bool deserialize(SPSInputBuffer &IB, PerfJITRecordPrefix &Val) { in deserialize() argument
101 if (!SPSPerfJITRecordPrefix::AsArgList::deserialize(IB, Id, Val.TotalSize)) in deserialize()
103 Val.Id = static_cast<PerfJITRecordType>(Id); in deserialize()
106 static bool serialize(SPSOutputBuffer &OB, const PerfJITRecordPrefix &Val) { in serialize() argument
108 OB, static_cast<uint32_t>(Val.Id), Val.TotalSize); in serialize()
119 static size_t size(const PerfJITCodeLoadRecord &Val) { in size() argument
121 Val.Prefix, Val.Pid, Val.Tid, Val.Vma, Val.CodeAddr, Val.CodeSize, in size()
122 Val.CodeIndex, Val.Name); in size()
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/llvm-project/llvm/include/llvm/ADT/
H A DTinyPtrVector.h40 PtrUnion Val;
46 if (VecTy *V = dyn_cast_if_present<VecTy *>(Val)) in ~TinyPtrVector()
50 TinyPtrVector(const TinyPtrVector &RHS) : Val(RHS.Val) { in TinyPtrVector()
51 if (VecTy *V = dyn_cast_if_present<VecTy *>(Val)) in TinyPtrVector()
52 Val = new VecTy(*V); in TinyPtrVector()
65 if (isa<EltTy>(Val)) {
67 Val = RHS.front();
69 Val = new VecTy(*cast<VecTy *>(RHS.Val));
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H A DDenseMapInfo.h73 uintptr_t Val = static_cast<uintptr_t>(-1);
74 Val <<= Log2MaxAlign;
75 return reinterpret_cast<T*>(Val);
79 uintptr_t Val = static_cast<uintptr_t>(-2);
80 Val <<= Log2MaxAlign;
81 return reinterpret_cast<T*>(Val);
96 static unsigned getHashValue(const char& Val) { return Val * 37U; }
107 static unsigned getHashValue(const unsigned char &Val) { return Val * 37U; }
118 static unsigned getHashValue(const unsigned short &Val) { return Val * 37U; }
129 static unsigned getHashValue(const unsigned& Val) { return Val * 37U; }
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/llvm-project/llvm/unittests/ADT/
H A DAPFixedPointTest.cpp282 APFixedPoint Val(Representation, Sema); in CheckIntPartRes()
283 ASSERT_EQ(Val.getIntPart().getZExtValue(), Result) ; in CheckIntPartRes()
698 APFixedPoint Val = APFixedPoint(1ULL << 7, getSAccumSema()); in TEST()
699 ASSERT_EQ(Val.convert(getLFractSema()).getValue(), -(1ULL << 31)); in TEST()
701 Val = APFixedPoint(1ULL << 23, getAccumSema()); in TEST()
702 ASSERT_EQ(Val.convert(getSAccumSema()).getValue(), -(1ULL << 15)); in TEST()
704 Val = APFixedPoint(1ULL << 47, getLAccumSema()); in TEST()
705 ASSERT_EQ(Val.convert(getAccumSema()).getValue(), -(1ULL << 31)); in TEST()
708 Val = APFixedPoint(/*-1.5*/ -192, getSAccumSema()); in TEST()
709 ASSERT_EQ(Val in TEST()
281 APFixedPoint Val(Representation, Sema); CheckIntPartRes() local
697 APFixedPoint Val = APFixedPoint(1ULL << 7, getSAccumSema()); TEST() local
730 CheckFloatToFixedConversion(APFloat & Val,const FixedPointSemantics & Sema,int64_t ExpectedNonSat) CheckFloatToFixedConversion() argument
742 CheckFloatToFixedConversion(APFloat & Val,const FixedPointSemantics & Sema,OvfKind ExpectedOvf) CheckFloatToFixedConversion() argument
776 APFloat Val(0.0f); TEST() local
978 CheckFixedToFloatConversion(int64_t Val,const FixedPointSemantics & Sema,float Result) CheckFixedToFloatConversion() argument
985 CheckFixedToHalfConversion(int64_t Val,const FixedPointSemantics & Sema,float Result) CheckFixedToHalfConversion() argument
995 int64_t Val = 0x1ULL; TEST() local
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/llvm-project/llvm/lib/Support/
H A DSlowDynamicAPInt.cpp17 SlowDynamicAPInt::SlowDynamicAPInt(int64_t Val) in SlowDynamicAPInt() argument
18 : Val(64, Val, /*isSigned=*/true) {} in SlowDynamicAPInt()
20 SlowDynamicAPInt::SlowDynamicAPInt(const APInt &Val) : Val(Val) {} in SlowDynamicAPInt() argument
21 SlowDynamicAPInt &SlowDynamicAPInt::operator=(int64_t Val) { in operator =() argument
22 return *this = SlowDynamicAPInt(Val); in operator =()
24 SlowDynamicAPInt::operator int64_t() const { return Val.getSExtValue(); } in operator int64_t()
27 return hash_value(X.Val); in hash_value()
127 unsigned Width = getMaxWidth(Val, O.Val); in operator ==()
128 return Val.sext(Width) == O.Val.sext(Width); in operator ==()
131 unsigned Width = getMaxWidth(Val, O.Val); in operator !=()
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/llvm-project/clang/test/CodeGen/SystemZ/
H A Dgnu-atomic-builtins-i16.c34 void f3(int16_t *Ptr, int16_t Val) { in f3() argument
35 __atomic_store_n(Ptr, Val, memory_order_seq_cst); in f3()
44 void f4(int16_t *Ptr, int16_t *Val) { in f4() argument
45 __atomic_store(Ptr, Val, memory_order_seq_cst); in f4()
53 int16_t f5(int16_t *Ptr, int16_t Val) { in f5() argument
54 return __atomic_exchange_n(Ptr, Val, memory_order_seq_cst); in f5()
64 int16_t f6(int16_t *Ptr, int16_t *Val, int16_t *Ret) { in f6() argument
65 __atomic_exchange(Ptr, Val, Ret, memory_order_seq_cst); in f6()
112 int16_t f9(int16_t *Ptr, int16_t Val) { in f9() argument
113 return __atomic_add_fetch(Ptr, Val, memory_order_seq_cst); in f9()
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H A Dgnu-atomic-builtins-i64.c34 void f3(int64_t *Ptr, int64_t Val) { in f3() argument
35 __atomic_store_n(Ptr, Val, memory_order_seq_cst); in f3()
44 void f4(int64_t *Ptr, int64_t *Val) { in f4() argument
45 __atomic_store(Ptr, Val, memory_order_seq_cst); in f4()
53 int64_t f5(int64_t *Ptr, int64_t Val) { in f5() argument
54 return __atomic_exchange_n(Ptr, Val, memory_order_seq_cst); in f5()
64 int64_t f6(int64_t *Ptr, int64_t *Val, int64_t *Ret) { in f6() argument
65 __atomic_exchange(Ptr, Val, Ret, memory_order_seq_cst); in f6()
112 int64_t f9(int64_t *Ptr, int64_t Val) { in f9() argument
113 return __atomic_add_fetch(Ptr, Val, memory_order_seq_cst); in f9()
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H A Dgnu-atomic-builtins-i32.c34 void f3(int32_t *Ptr, int32_t Val) { in f3() argument
35 __atomic_store_n(Ptr, Val, memory_order_seq_cst); in f3()
44 void f4(int32_t *Ptr, int32_t *Val) { in f4() argument
45 __atomic_store(Ptr, Val, memory_order_seq_cst); in f4()
53 int32_t f5(int32_t *Ptr, int32_t Val) { in f5() argument
54 return __atomic_exchange_n(Ptr, Val, memory_order_seq_cst); in f5()
64 int32_t f6(int32_t *Ptr, int32_t *Val, int32_t *Ret) { in f6() argument
65 __atomic_exchange(Ptr, Val, Ret, memory_order_seq_cst); in f6()
112 int32_t f9(int32_t *Ptr, int32_t Val) { in f9() argument
113 return __atomic_add_fetch(Ptr, Val, memory_order_seq_cst); in f9()
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H A Dgnu-atomic-builtins-i8.c34 void f3(int8_t *Ptr, int8_t Val) { in f3() argument
35 __atomic_store_n(Ptr, Val, memory_order_seq_cst); in f3()
44 void f4(int8_t *Ptr, int8_t *Val) { in f4() argument
45 __atomic_store(Ptr, Val, memory_order_seq_cst); in f4()
53 int8_t f5(int8_t *Ptr, int8_t Val) { in f5() argument
54 return __atomic_exchange_n(Ptr, Val, memory_order_seq_cst); in f5()
64 int8_t f6(int8_t *Ptr, int8_t *Val, int8_t *Ret) { in f6() argument
65 __atomic_exchange(Ptr, Val, Ret, memory_order_seq_cst); in f6()
112 int8_t f9(int8_t *Ptr, int8_t Val) { in f9() argument
113 return __atomic_add_fetch(Ptr, Val, memory_order_seq_cst); in f9()
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H A Dsync-builtins-i128-16Al.c10 __int128 Val __attribute__((aligned(16))); variable
21 return __sync_fetch_and_add(&Ptr, Val); in f1()
32 return __sync_fetch_and_sub(&Ptr, Val); in f2()
43 return __sync_fetch_and_or(&Ptr, Val); in f3()
54 return __sync_fetch_and_and(&Ptr, Val); in f4()
65 return __sync_fetch_and_xor(&Ptr, Val); in f5()
76 return __sync_fetch_and_nand(&Ptr, Val); in f6()
88 return __sync_add_and_fetch(&Ptr, Val); in f7()
100 return __sync_sub_and_fetch(&Ptr, Val); in f8()
112 return __sync_or_and_fetch(&Ptr, Val); in f9()
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H A Dgnu-atomic-builtins-i128-8Al.c12 __int128 Val; variable
50 __atomic_store_n(&Ptr, Val, memory_order_seq_cst); in f3()
60 __atomic_store(&Ptr, &Val, memory_order_seq_cst); in f4()
71 return __atomic_exchange_n(&Ptr, Val, memory_order_seq_cst); in f5()
83 __atomic_exchange(&Ptr, &Val, &Ret, memory_order_seq_cst); in f6()
134 return __atomic_add_fetch(&Ptr, Val, memory_order_seq_cst); in f9()
146 return __atomic_sub_fetch(&Ptr, Val, memory_order_seq_cst); in f10()
158 return __atomic_and_fetch(&Ptr, Val, memory_order_seq_cst); in f11()
170 return __atomic_xor_fetch(&Ptr, Val, memory_order_seq_cst); in f12()
182 return __atomic_or_fetch(&Ptr, Val, memory_order_seq_cst); in f13()
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H A Dgnu-atomic-builtins-i128-16Al.c12 __int128 Val __attribute__((aligned(16))); variable
45 __atomic_store_n(&Ptr, Val, memory_order_seq_cst); in f3()
55 __atomic_store(&Ptr, &Val, memory_order_seq_cst); in f4()
66 return __atomic_exchange_n(&Ptr, Val, memory_order_seq_cst); in f5()
78 __atomic_exchange(&Ptr, &Val, &Ret, memory_order_seq_cst); in f6()
129 return __atomic_add_fetch(&Ptr, Val, memory_order_seq_cst); in f9()
141 return __atomic_sub_fetch(&Ptr, Val, memory_order_seq_cst); in f10()
153 return __atomic_and_fetch(&Ptr, Val, memory_order_seq_cst); in f11()
165 return __atomic_xor_fetch(&Ptr, Val, memory_order_seq_cst); in f12()
177 return __atomic_or_fetch(&Ptr, Val, memory_order_seq_cst); in f13()
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/llvm-project/llvm/include/llvm/Support/
H A DCasting.h38 static SimpleType &getSimplifiedValue(From &Val) { return Val; } in getSimplifiedValue()
47 static RetType getSimplifiedValue(const From &Val) {
48 return simplify_type<From>::getSimplifiedValue(const_cast<From &>(Val));
64 static inline bool doit(const From &Val) { return To::classof(&Val); }
74 static inline bool doit(const From &Val) {
75 return isa_impl<To, From>::doit(Val);
80 static inline bool doit(const From &Val) {
81 return isa_impl<To, From>::doit(Val);
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/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMatInt.cpp49 static void generateInstSeqImpl(int64_t Val, const MCSubtargetInfo &STI, in generateInstSeqImpl() argument
54 if (STI.hasFeature(RISCV::FeatureStdExtZbs) && isPowerOf2_64(Val) && in generateInstSeqImpl()
55 (!isInt<32>(Val) || Val == 0x800)) { in generateInstSeqImpl()
56 Res.emplace_back(RISCV::BSETI, Log2_64(Val)); in generateInstSeqImpl()
60 if (isInt<32>(Val)) { in generateInstSeqImpl()
68 int64_t Hi20 = ((Val + 0x800) >> 12) & 0xFFFFF; in generateInstSeqImpl()
69 int64_t Lo12 = SignExtend64<12>(Val); in generateInstSeqImpl()
106 int64_t Lo12 = SignExtend64<12>(Val); in generateInstSeqImpl()
107 Val in generateInstSeqImpl()
158 extractRotateInfo(int64_t Val) extractRotateInfo() argument
176 generateInstSeqLeadingZeros(int64_t Val,const MCSubtargetInfo & STI,RISCVMatInt::InstSeq & Res) generateInstSeqLeadingZeros() argument
227 generateInstSeq(int64_t Val,const MCSubtargetInfo & STI) generateInstSeq() argument
431 generateMCInstSeq(int64_t Val,const MCSubtargetInfo & STI,MCRegister DestReg,SmallVectorImpl<MCInst> & Insts) generateMCInstSeq() argument
468 generateTwoRegInstSeq(int64_t Val,const MCSubtargetInfo & STI,unsigned & ShiftAmt,unsigned & AddOpc) generateTwoRegInstSeq() argument
501 getIntMatCost(const APInt & Val,unsigned Size,const MCSubtargetInfo & STI,bool CompressionCost) getIntMatCost() argument
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/llvm-project/clang/lib/Lex/
H A DPPExpressions.cpp49 llvm::APSInt Val;
52 PPValue(unsigned BitWidth) : Val(BitWidth) {}
59 unsigned getBitWidth() const { return Val.getBitWidth(); }
60 bool isUnsigned() const { return Val.isUnsigned(); } in getBitWidth()
131 Result.Val = !!Macro; in EvaluateDefined()
132 Result.Val.setIsUnsigned(false); // Result is signed intmax_t. in EvaluateDefined()
140 if (Result.Val != 0 && ValueLive) in EvaluateDefined()
277 Result.Val = 0; in EvaluateValue()
278 Result.Val.setIsUnsigned(false); // "0" is signed intmax_t 0. in EvaluateValue()
344 if (Literal.GetIntegerValue(Result.Val)) { in EvaluateValue()
50 llvm::APSInt Val; global() member in __anon289ca2080111::PPValue
409 llvm::APSInt Val(NumBits); EvaluateValue() local
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/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUPALMetadata.h58 void setRsrc1(unsigned CC, unsigned Val);
59 void setRsrc1(unsigned CC, const MCExpr *Val, MCContext &Ctx);
63 void setRsrc2(unsigned CC, unsigned Val);
64 void setRsrc2(unsigned CC, const MCExpr *Val, MCContext &Ctx);
68 void setSpiPsInputEna(unsigned Val);
72 void setSpiPsInputAddr(unsigned Val);
79 void setRegister(unsigned Reg, unsigned Val);
80 void setRegister(unsigned Reg, const MCExpr *Val, MCContext &Ctx);
88 void setNumUsedVgprs(unsigned CC, unsigned Val);
89 void setNumUsedVgprs(unsigned CC, const MCExpr *Val, MCContext &Ctx);
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H A DAMDGPUPALMetadata.cpp60 auto *Val = mdconst::dyn_extract<ConstantInt>(Tuple->getOperand(I + 1)); in readFromIR() local
61 if (!Key || !Val) in readFromIR()
63 setRegister(Key->getZExtValue(), Val->getZExtValue()); in readFromIR()
137 void AMDGPUPALMetadata::setRsrc1(CallingConv::ID CC, unsigned Val) { in setRsrc1() argument
138 setRegister(getRsrc1Reg(CC), Val); in setRsrc1()
141 void AMDGPUPALMetadata::setRsrc1(CallingConv::ID CC, const MCExpr *Val, in setRsrc1() argument
143 setRegister(getRsrc1Reg(CC), Val, Ctx); in setRsrc1()
148 void AMDGPUPALMetadata::setRsrc2(CallingConv::ID CC, unsigned Val) { in setRsrc2() argument
149 setRegister(getRsrc1Reg(CC) + 1, Val); in setRsrc2()
152 void AMDGPUPALMetadata::setRsrc2(CallingConv::ID CC, const MCExpr *Val, in setRsrc2() argument
159 setSpiPsInputEna(unsigned Val) setSpiPsInputEna() argument
165 setSpiPsInputAddr(unsigned Val) setSpiPsInputAddr() argument
183 setRegister(unsigned Reg,unsigned Val) setRegister() argument
198 setRegister(unsigned Reg,const MCExpr * Val,MCContext & Ctx) setRegister() argument
242 setNumUsedVgprs(CallingConv::ID CC,unsigned Val) setNumUsedVgprs() argument
255 setNumUsedVgprs(CallingConv::ID CC,const MCExpr * Val,MCContext & Ctx) setNumUsedVgprs() argument
270 setNumUsedAgprs(CallingConv::ID CC,unsigned Val) setNumUsedAgprs() argument
274 setNumUsedAgprs(unsigned CC,const MCExpr * Val) setNumUsedAgprs() argument
281 setNumUsedSgprs(CallingConv::ID CC,unsigned Val) setNumUsedSgprs() argument
294 setNumUsedSgprs(unsigned CC,const MCExpr * Val,MCContext & Ctx) setNumUsedSgprs() argument
309 setScratchSize(CallingConv::ID CC,unsigned Val) setScratchSize() argument
319 setScratchSize(unsigned CC,const MCExpr * Val,MCContext & Ctx) setScratchSize() argument
331 setFunctionScratchSize(StringRef FnName,unsigned Val) setFunctionScratchSize() argument
338 setFunctionLdsSize(StringRef FnName,unsigned Val) setFunctionLdsSize() argument
345 setFunctionNumUsedVgprs(StringRef FnName,unsigned Val) setFunctionNumUsedVgprs() argument
351 setFunctionNumUsedVgprs(StringRef FnName,const MCExpr * Val) setFunctionNumUsedVgprs() argument
358 setFunctionNumUsedSgprs(StringRef FnName,unsigned Val) setFunctionNumUsedSgprs() argument
364 setFunctionNumUsedSgprs(StringRef FnName,const MCExpr * Val) setFunctionNumUsedSgprs() argument
777 unsigned Val = I->second.getUInt(); toString() local
858 uint64_t Val; setFromString() local
1045 setHwStage(unsigned CC,StringRef field,unsigned Val) setHwStage() argument
1049 setHwStage(unsigned CC,StringRef field,bool Val) setHwStage() argument
1054 setHwStage(unsigned CC,StringRef field,msgpack::Type Type,const MCExpr * Val) setHwStage() argument
1058 setComputeRegisters(StringRef field,unsigned Val) setComputeRegisters() argument
1062 setComputeRegisters(StringRef field,bool Val) setComputeRegisters() argument
1072 checkComputeRegisters(StringRef field,unsigned Val) checkComputeRegisters() argument
1078 checkComputeRegisters(StringRef field,bool Val) checkComputeRegisters() argument
1084 setGraphicsRegisters(StringRef field,unsigned Val) setGraphicsRegisters() argument
1088 setGraphicsRegisters(StringRef field,bool Val) setGraphicsRegisters() argument
1093 setGraphicsRegisters(StringRef field1,StringRef field2,unsigned Val) setGraphicsRegisters() argument
1098 setGraphicsRegisters(StringRef field1,StringRef field2,bool Val) setGraphicsRegisters() argument
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/llvm-project/llvm/lib/Transforms/Utils/
H A DLowerAtomic.cpp26 Value *Val = CXI->getNewValOperand(); in lowerAtomicCmpXchgInst() local
29 buildCmpXchgValue(Builder, Ptr, Cmp, Val, CXI->getAlign()); in lowerAtomicCmpXchgInst()
42 Value *Val, in buildAtomicRMWValue()
44 LoadInst *Orig = Builder.CreateAlignedLoad(Val->getType(), Ptr, Alignment); in buildAtomicRMWValue()
46 Value *Res = Builder.CreateSelect(Equal, Val, Orig); in buildAtomicRMWValue()
54 Value *Val) { in buildAtomicRMWValue()
58 return Val; in buildAtomicRMWValue()
60 return Builder.CreateAdd(Loaded, Val, "new"); in buildAtomicRMWValue()
62 return Builder.CreateSub(Loaded, Val, "new"); in buildAtomicRMWValue()
64 return Builder.CreateAnd(Loaded, Val, "ne in buildAtomicRMWValue()
43 buildAtomicRMWValue(AtomicRMWInst::BinOp Op,IRBuilderBase & Builder,Value * Loaded,Value * Val) buildAtomicRMWValue() argument
108 Value *Val = RMWI->getValOperand(); lowerAtomicRMWInst() local
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/llvm-project/compiler-rt/lib/orc/
H A Dstl_extras.h33 constexpr uint64_t bit_ceil(uint64_t Val) noexcept { in bit_ceil() argument
34 Val |= (Val >> 1); in bit_ceil()
35 Val |= (Val >> 2); in bit_ceil()
36 Val |= (Val >> 4); in bit_ceil()
37 Val |= (Val >> 8); in bit_ceil()
38 Val | in bit_ceil()
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/llvm-project/compiler-rt/lib/ubsan/
H A Dubsan_value.cpp70 // Val was zero-extended to ValueHandle. Sign-extend from original width in getSIntValue()
75 return SIntMax(UIntMax(Val) << ExtraBits) >> ExtraBits; in getSIntValue()
78 return SIntMax(UIntMax(*reinterpret_cast<s64 *>(Val)) << ExtraBits) >> in getSIntValue()
83 return SIntMax(UIntMax(*reinterpret_cast<s128 *>(Val)) << ExtraBits) >> in getSIntValue()
95 return Val; in getUIntValue()
97 return *reinterpret_cast<u64*>(Val); in getUIntValue()
100 return *reinterpret_cast<u128*>(Val); in getUIntValue()
111 SIntMax Val = getSIntValue(); in getPositiveIntValue()
112 CHECK(Val >= 0);
113 return Val;
108 SIntMax Val = getSIntValue(); getPositiveIntValue() local
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/llvm-project/compiler-rt/lib/sanitizer_common/
H A Dsanitizer_dense_map_info.h84 uptr Val = static_cast<uptr>(-1);
85 Val <<= Log2MaxAlign;
86 return reinterpret_cast<T *>(Val);
90 uptr Val = static_cast<uptr>(-2);
91 Val <<= Log2MaxAlign;
92 return reinterpret_cast<T *>(Val);
109 static constexpr unsigned getHashValue(const char &Val) { return Val * 37U; }
121 static constexpr unsigned getHashValue(const unsigned char &Val) {
122 return Val * 37U;
136 static constexpr unsigned getHashValue(const unsigned short &Val) {
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/llvm-project/llvm/lib/Target/VE/
H A DVE.h205 inline static VECC::CondCode VEValToCondCode(unsigned Val, bool IsInteger) { in VEValToCondCode() argument
207 switch (Val) { in VEValToCondCode()
226 switch (Val) { in VEValToCondCode()
309 inline static VERD::RoundingMode VEValToRD(unsigned Val) { in VEValToRD() argument
310 switch (Val) { in VEValToRD()
331 inline static bool isMImmVal(uint64_t Val) { in isMImmVal() argument
332 if (Val == 0) { in isMImmVal()
336 if (isMask_64(Val)) { in isMImmVal()
341 return (Val & (UINT64_C(1) << 63)) && isShiftedMask_64(Val); in isMImmVal()
344 inline static bool isMImm32Val(uint32_t Val) { in isMImm32Val() argument
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/llvm-project/llvm/test/TableGen/
H A Dsize.td9 // CHECK: int Val = 0;
13 // CHECK: int Val = 3;
17 // CHECK: int Val = 0;
21 // CHECK: int Val = 2;
25 int Val = !size(L);
29 int Val = !size(L);
41 // CHECK: int Val = 0;
45 // CHECK: int Val = 1;
49 // CHECK: int Val = 2;
53 // CHECK: int Val = 3;
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/llvm-project/clang/test/Analysis/
H A Dcxx-uninitialized-object-unionlike-constructs.cpp32 UnionLikeStruct1(Kind kind, int Val) : kind(kind) { in UnionLikeStruct1()
35 Volume = Val; in UnionLikeStruct1()
38 Area = Val; in UnionLikeStruct1()
58 UnionLikeStruct2(Type kind, int Val) : kind(kind) { in UnionLikeStruct2()
61 Volume = Val; in UnionLikeStruct2()
64 Area = Val; in UnionLikeStruct2()
84 UnionLikeStruct3(Kind type, int Val) : type(type) { in UnionLikeStruct3()
87 Volume = Val; in UnionLikeStruct3()
90 Area = Val; in UnionLikeStruct3()
110 UnionLikeStruct4(Tag type, int Val) : type(type) { in UnionLikeStruct4()
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/llvm-project/llvm/lib/MC/
H A DMCSymbolELF.cpp45 unsigned Val; in setBinding() local
50 Val = 0; in setBinding()
53 Val = 1; in setBinding()
56 Val = 2; in setBinding()
59 Val = 3; in setBinding()
63 setFlags(OtherFlags | (Val << ELF_STB_Shift)); in setBinding()
68 uint32_t Val = (Flags >> ELF_STB_Shift) & 3; in getBinding() local
69 switch (Val) { in getBinding()
95 unsigned Val; in setType() local
100 Val = 0; in setType()
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