Searched refs:RegisterMask (Results 1 – 9 of 9) sorted by relevance
| /llvm-project/llvm/lib/MCA/Stages/ |
| H A D | DispatchStage.cpp | 51 const unsigned RegisterMask = PRF.isAvailable(RegDefs); in checkPRF() local
53 if (RegisterMask) { in checkPRF()
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| /llvm-project/llvm/tools/llvm-readobj/ |
| H A D | ARMWinEHPrinter.cpp | 342 uint16_t RegisterMask = (Link << (Prologue ? 14 : 15)) in opcode_10Lxxxxx() local
345 assert((~RegisterMask & (1 << 13)) && "sp must not be set"); in opcode_10Lxxxxx()
346 assert((~RegisterMask & (1 << (Prologue ? 15 : 14))) && "pc must not be set"); in opcode_10Lxxxxx()
351 printGPRMask(RegisterMask); in opcode_10Lxxxxx()
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| /llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 75 RegisterMask, enumerator
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| H A D | SelectionDAGNodes.h | 2303 : SDNode(ISD::RegisterMask, 0, DebugLoc(), getSDVTList(MVT::Untyped)),
2310 return N->getOpcode() == ISD::RegisterMask;
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| /llvm-project/libunwind/src/ |
| H A D | Unwind-EHABI.cpp | 202 uint32_t RegisterMask(uint8_t start, uint8_t count_minus_one) { in RegisterMask() function
302 uint32_t registers = RegisterMask(4, byte & 0x07); in _Unwind_VRS_Interpret()
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| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 127 case ISD::RegisterMask: return "RegisterMask"; in getOperationName()
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| H A D | SelectionDAGISel.cpp | 3240 case ISD::RegisterMask: in SelectCodeCommon()
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| H A D | SelectionDAG.cpp | 788 case ISD::RegisterMask: in AddNodeIDCustom()
2346 AddNodeIDNode(ID, ISD::RegisterMask, getVTList(MVT::Untyped), {}); in getSrcValue()
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| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 4197 SDValue RegisterMask = DAG.getRegisterMask(Mask); in LowerINTRINSIC_WO_CHAIN()
4203 DAG.getRegister(0, PtrVT), Callee, RegisterMask, Chain}), in LowerINTRINSIC_WO_CHAIN()
4207 {ReturnAddress, Callee, RegisterMask, Chain}), in LowerINTRINSIC_WO_CHAIN()
4120 SDValue RegisterMask = DAG.getRegisterMask(Mask); LowerINTRINSIC_VOID() local
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