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Searched refs:RVC (Results 1 – 10 of 10) sorted by relevance

/llvm-project/llvm/test/MC/RISCV/
H A Dnop-slide.s1 … +c,-relax -filetype obj -o - %s | llvm-objdump -d - | FileCheck %s -check-prefix CHECK-RVC-NORELAX
2 …tr +c,+relax -filetype obj -o - %s | llvm-objdump -d - | FileCheck %s -check-prefix CHECK-RVC-RELAX
12 # CHECK-RVC-NORELAX: 0000000000000000 <.text>:
13 # CHECK-RVC-NORELAX-NEXT: 0: 0000 unimp
14 # CHECK-RVC-NORELAX-NEXT: 2: 0001 nop
15 # CHECK-RVC-NORELAX-NEXT: 4: 00000517 auipc a0, 0x0
17 # CHECK-RVC-RELAX: 0000000000000000 <.text>:
18 # CHECK-RVC-RELAX-NEXT: 0: 0001 nop
19 # CHECK-RVC-RELAX-NEXT: 2: 0100 addi s0, sp, 0x80
20 # CHECK-RVC-RELAX-NEXT: 4: 1700 addi s0, sp, 0x3a0
[all …]
H A Drv32c-invalid.s27 c.li zero, 2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RVC Hint Instructio…
29 c.mv zero, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RVC Hint Instructi…
35 c.lui x0, 4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RVC Hint Instructions…
60 c.addi t0, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RVC Hint Instruction…
/llvm-project/lld/test/ELF/
H A Driscv-relax-call.s6 ## Without RVC
19 ## RVC
24 # RUN: llvm-objdump -td --no-show-raw-insn -M no-aliases 32c | FileCheck %s --check-prefixes=RVC,RV…
30 # RUN: llvm-objdump -td --no-show-raw-insn -M no-aliases 64c | FileCheck %s --check-prefixes=RVC,RV…
75 # RVC-LABEL: <_start>:
76 # RVC-NEXT: 10000: c.j {{.*}} <a>
77 # RVC-NEXT: c.j {{.*}} <a>
78 # RVC-NEXT: addi zero, zero, 0x0
79 # RVC-NEXT: addi zero, zero, 0x0
80 # RVC-NEXT: addi zero, zero, 0x0
[all …]
/llvm-project/llvm/test/CodeGen/RISCV/
H A Dpatchable-function-entry.ll4 …c -mtriple=riscv32 -mattr=+c --riscv-no-aliases < %s | FileCheck %s --check-prefixes=CHECK,RV32,RVC
5 …c -mtriple=riscv64 -mattr=+c --riscv-no-aliases < %s | FileCheck %s --check-prefixes=CHECK,RV64,RVC
12 ; RVC: c.jr ra
22 ; RVC: c.nop
23 ; RVC-NEXT: c.jr ra
38 ; RVC-COUNT-5: c.nop
39 ; RVC-NEXT: c.jr ra
54 ; RVC-COUNT-2: c.nop
59 ; RVC-NEXT: c.nop
60 ; RVC-NEXT: c.addi sp, -16
H A Dmodule-elf-flags.ll3 ; FLAGS: Flags: 0x11, RVC, TSO
/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMCObjectFileInfo.cpp22 bool RVC = STI.hasFeature(RISCV::FeatureStdExtC) || in getTextSectionAlignment() local
24 return RVC ? 2 : 4; in getTextSectionAlignment()
/llvm-project/bolt/test/RISCV/
H A Dfunction-alignment.s1 ## Test that BOLT uses a minimum function alignment of 4 (or 2 for RVC) bytes.
/llvm-project/llvm/test/ExecutionEngine/JITLink/RISCV/
H A DELF_relax_call.s45 ## Successful relaxation: jump -> jal (not c.j as RVC is disabled)
/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVFeatures.td364 "Disable RVC Hint Instructions.">;
367 "RVC Hint Instructions">;
H A DRISCVInstrInfoC.td856 // under the "RVC Instruction Set Listings" section of the ISA manual.