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Searched refs:MachineInstr (Results 1 – 25 of 847) sorted by relevance

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/freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DCombinerHelper.h38 class MachineInstr; variable
52 MachineInstr *MI;
76 MachineInstr *Logic;
77 MachineInstr *Shift2;
156 void replaceOpcodeWith(MachineInstr &FromMI, unsigned ToOpcode) const;
172 bool tryCombineCopy(MachineInstr &MI);
173 bool matchCombineCopy(MachineInstr &MI);
174 void applyCombineCopy(MachineInstr &MI);
178 bool isPredecessor(const MachineInstr &DefMI, const MachineInstr
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H A DLegalizerHelper.h37 class MachineInstr; variable
94 LegalizeResult legalizeInstrStep(MachineInstr &MI,
98 LegalizeResult libcall(MachineInstr &MI, LostDebugLocObserver &LocObserver);
102 LegalizeResult narrowScalar(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy);
107 LegalizeResult widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
110 LegalizeResult bitcast(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
114 LegalizeResult lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
118 LegalizeResult fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
123 LegalizeResult moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
137 void widenScalarSrc(MachineInstr
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.h34 class MachineInstr; variable
57 Register isLoadFromStackSlot(const MachineInstr &MI,
65 Register isStoreToStackSlot(const MachineInstr &MI,
72 const MachineInstr &MI,
79 const MachineInstr &MI,
205 bool expandPostRAPseudo(MachineInstr &MI) const override;
209 const MachineInstr &LdSt,
224 bool isPredicated(const MachineInstr &MI) const override;
227 bool isPostIncrement(const MachineInstr &MI) const override;
231 bool PredicateInstruction(MachineInstr
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H A DHexagonVLIWPacketizer.h23 class MachineInstr; variable
29 std::vector<MachineInstr *> OldPacketMIs;
54 std::vector<MachineInstr*> IgnoreDepMIs;
89 bool ignorePseudoInstruction(const MachineInstr &MI,
94 bool isSoloInstruction(const MachineInstr &MI) override;
105 MachineBasicBlock::iterator addToPacket(MachineInstr &MI) override;
108 bool shouldAddToPacket(const MachineInstr &MI) override;
119 bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType,
121 bool promoteToDotCur(MachineInstr &MI, SDep::Kind DepType,
124 bool canPromoteToDotCur(const MachineInstr &MI, const SUnit *PacketSU,
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNHazardRecognizer.h25 class MachineInstr; variable
34 typedef function_ref<bool(const MachineInstr &)> IsHazardFn;
43 MachineInstr *CurrCycleInstr;
44 std::list<MachineInstr*> EmittedInstrs;
63 void addClauseInst(const MachineInstr &MI);
67 unsigned getMFMAPipelineWaitStates(const MachineInstr &MI) const;
69 // Advance over a MachineInstr bundle. Look for hazards in the bundled
75 void runOnInstruction(MachineInstr *MI);
81 int checkSoftClauseHazards(MachineInstr *SMEM);
82 int checkSMRDHazards(MachineInstr *SMR
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H A DAMDGPULegalizerInfo.h37 bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI,
44 bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI,
46 bool legalizeFroundeven(MachineInstr &MI, MachineRegisterInfo &MRI,
48 bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
50 bool legalizeFrem(MachineInstr &MI, MachineRegisterInfo &MRI,
52 bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
54 bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
56 bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
58 bool legalizeMinNumMaxNum(LegalizerHelper &Helper, MachineInstr &MI) const;
59 bool legalizeExtractVectorElt(MachineInstr
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H A DAMDGPUInstructionSelector.h39 class MachineInstr; variable
58 bool select(MachineInstr &I) override;
74 bool isInstrUniform(const MachineInstr &MI) const;
82 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
88 bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const;
89 bool selectCOPY(MachineInstr &I) const;
90 bool selectPHI(MachineInstr &I) const;
91 bool selectG_TRUNC(MachineInstr &I) const;
92 bool selectG_SZA_EXT(MachineInstr &I) const;
93 bool selectG_FPEXT(MachineInstr
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H A DSIInstrInfo.h52 void insert(MachineInstr *MI);
54 MachineInstr *top() const { in top()
71 bool isDeferred(MachineInstr *MI);
73 SetVector<MachineInstr *> &getDeferredList() { return DeferredList; } in getDeferredList()
77 SetVector<MachineInstr *> InstrList;
78 /// Deferred instructions are specific MachineInstr
80 SetVector<MachineInstr *> DeferredList;
101 using SetVectorType = SmallSetVector<MachineInstr *, 32>;
119 void swapOperands(MachineInstr &Inst) const;
122 moveScalarAddSub(SIInstrWorklist &Worklist, MachineInstr
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H A DR600InstrInfo.h34 class MachineInstr; variable
44 ExtractSrcs(MachineInstr &MI, const DenseMap<unsigned, unsigned> &PV,
91 bool canBeConsideredALU(const MachineInstr &MI) const;
94 bool isTransOnly(const MachineInstr &MI) const;
96 bool isVectorOnly(const MachineInstr &MI) const;
100 bool usesVertexCache(const MachineInstr &MI) const;
102 bool usesTextureCache(const MachineInstr &MI) const;
105 bool usesAddressRegister(MachineInstr &MI) const;
106 bool definesAddressRegister(MachineInstr &MI) const;
107 bool readsLDSSrcReg(const MachineInstr &MI) const;
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrInfo.h39 AC_EVEX_2_LEGACY = MachineInstr::TAsmComments,
60 CondCode getCondFromMI(const MachineInstr &MI);
63 CondCode getCondFromBranch(const MachineInstr &MI);
66 CondCode getCondFromSETCC(const MachineInstr &MI);
69 CondCode getCondFromCMov(const MachineInstr &MI);
72 CondCode getCondFromCFCMov(const MachineInstr &MI);
75 CondCode getCondFromCCMP(const MachineInstr &MI);
106 bool isX87Instruction(MachineInstr &MI); in isGlobalStubReference()
112 int getFirstAddrOperandIdx(const MachineInstr &MI);
115 const Constant *getConstantFromPool(const MachineInstr in isGlobalRelativeToPICBase()
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H A DX86AsmPrinter.h82 void LowerSTACKMAP(const MachineInstr &MI);
83 void LowerPATCHPOINT(const MachineInstr &MI, X86MCInstLower &MCIL);
84 void LowerSTATEPOINT(const MachineInstr &MI, X86MCInstLower &MCIL);
85 void LowerFAULTING_OP(const MachineInstr &MI, X86MCInstLower &MCIL);
86 void LowerPATCHABLE_OP(const MachineInstr &MI, X86MCInstLower &MCIL);
88 void LowerTlsAddr(X86MCInstLower &MCInstLowering, const MachineInstr &MI);
91 void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI,
93 void LowerPATCHABLE_RET(const MachineInstr &MI, X86MCInstLower &MCIL);
94 void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI, X86MCInstLower &MCIL);
95 void LowerPATCHABLE_EVENT_CALL(const MachineInstr &MI, X86MCInstLower &MCIL);
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/freebsd-src/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h25 #include "llvm/CodeGen/MachineInstr.h"
143 bool isTriviallyReMaterializable(const MachineInstr &MI) const { in isTriviallyReMaterializable()
156 virtual bool isSafeToSink(MachineInstr &MI, MachineBasicBlock *SuccToSinkTo, in isSafeToSink()
168 virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const;
185 virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
214 bool isFrameInstr(const MachineInstr &I) const { in isFrameInstr()
220 bool isFrameSetup(const MachineInstr &I) const { in isFrameSetup()
232 int64_t getFrameSize(const MachineInstr &I) const { in getFrameSize()
241 int64_t getFrameTotalSize(const MachineInstr in getFrameTotalSize()
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H A DReachingDefAnalysis.h34 class MachineInstr; variable
94 DenseMap<MachineInstr *, int> InstIds;
107 using InstSet = SmallPtrSetImpl<MachineInstr*>;
142 int getReachingDef(MachineInstr *MI, MCRegister PhysReg) const;
145 bool hasSameReachingDef(MachineInstr *A, MachineInstr *B,
150 bool isReachingDefLiveOut(MachineInstr *MI, MCRegister PhysReg) const;
154 MachineInstr *getLocalLiveOutMIDef(MachineBasicBlock *MBB,
159 MachineInstr *getUniqueReachingMIDef(MachineInstr *MI,
164 MachineInstr *getMIOperand(MachineInstr *MI, unsigned Idx) const;
168 MachineInstr *getMIOperand(MachineInstr *MI, MachineOperand &MO) const;
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H A DModuloSchedule.h75 class MachineInstr; variable
88 std::vector<MachineInstr *> ScheduledInstrs;
91 DenseMap<MachineInstr *, int> Cycle;
94 DenseMap<MachineInstr *, int> Stage;
108 std::vector<MachineInstr *> ScheduledInstrs, in ModuloSchedule()
109 DenseMap<MachineInstr *, int> Cycle, in ModuloSchedule() argument
110 DenseMap<MachineInstr *, int> Stage) in ModuloSchedule()
135 int getStage(MachineInstr *MI) { in getStage()
141 int getCycle(MachineInstr *MI) { in getCycle()
147 void setStage(MachineInstr *M
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H A DLiveVariables.h37 #include "llvm/CodeGen/MachineInstr.h"
88 std::vector<MachineInstr*> Kills;
93 bool removeKill(MachineInstr &MI) {
94 std::vector<MachineInstr *>::iterator I = find(Kills, &MI);
102 MachineInstr *findKill(const MachineBasicBlock *MBB) const;
131 std::vector<MachineInstr *> PhysRegDef;
136 std::vector<MachineInstr *> PhysRegUse;
142 DenseMap<MachineInstr*, unsigned> DistanceMap;
152 bool HandlePhysRegKill(Register Reg, MachineInstr *MI);
157 void HandlePhysRegUse(Register Reg, MachineInstr
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsRegisterBankInfo.h39 getInstrMapping(const MachineInstr &MI) const override;
51 void setRegBank(MachineInstr &MI, MachineRegisterInfo &MRI) const;
126 SmallVector<MachineInstr *, 2> DefUses;
127 SmallVector<MachineInstr *, 2> UseDefs;
137 MachineInstr *skipCopiesOutgoing(MachineInstr *MI) const;
144 MachineInstr *skipCopiesIncoming(MachineInstr *MI) const;
147 AmbiguousRegDefUseContainer(const MachineInstr *MI);
148 SmallVectorImpl<MachineInstr *> &getDefUses() { return DefUses; } in getDefUses()
149 SmallVectorImpl<MachineInstr *> &getUseDefs() { return UseDefs; } in getUseDefs()
157 DenseMap<const MachineInstr *, SmallVector<const MachineInstr *, 2>>
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.h70 Register isLoadFromStackSlot(const MachineInstr &MI,
72 Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex,
74 Register isStoreToStackSlot(const MachineInstr &MI,
76 Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex,
79 bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
103 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
113 MachineInstr::MIFlag Flag = MachineInstr::NoFlags,
116 unsigned getInstSizeInBytes(const MachineInstr
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h184 SmallVectorImpl<MachineInstr *> &NewMIs) const;
188 SmallVectorImpl<MachineInstr *> &NewMIs) const;
192 bool simplifyToLI(MachineInstr &MI, MachineInstr &DefMI,
193 unsigned OpNoForForwarding, MachineInstr **KilledDef) const;
196 bool transformToNewImmFormFedByAdd(MachineInstr &MI, MachineInstr &DefMI,
200 bool transformToImmFormFedByLI(MachineInstr &MI, const ImmInstrInfo &III,
202 MachineInstr &DefMI) const;
205 bool transformToImmFormFedByAdd(MachineInstr
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.h188 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
190 bool isAsCheapAsAMove(const MachineInstr &MI) const override;
192 bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg,
196 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
197 const MachineInstr &MIb) const override;
199 Register isLoadFromStackSlot(const MachineInstr &MI,
201 Register isStoreToStackSlot(const MachineInstr &MI,
205 static bool isGPRZero(const MachineInstr &MI);
208 static bool isGPRCopy(const MachineInstr &MI);
211 static bool isFPRCopy(const MachineInstr
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64LegalizerInfo.h30 bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI,
34 MachineInstr &MI) const override;
37 bool legalizeVaArg(MachineInstr &MI, MachineRegisterInfo &MRI,
39 bool legalizeLoadStore(MachineInstr &MI, MachineRegisterInfo &MRI,
42 bool legalizeShlAshrLshr(MachineInstr &MI, MachineRegisterInfo &MRI,
46 bool legalizeSmallCMGlobalValue(MachineInstr &MI, MachineRegisterInfo &MRI,
49 bool legalizeBitfieldExtract(MachineInstr &MI, MachineRegisterInfo &MRI,
51 bool legalizeRotate(MachineInstr &MI, MachineRegisterInfo &MRI,
53 bool legalizeICMP(MachineInstr &MI, MachineRegisterInfo &MRI,
55 bool legalizeFunnelShift(MachineInstr
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCOptAddrMode.cpp21 #include "llvm/CodeGen/MachineInstr.h"
77 MachineInstr *tryToCombine(MachineInstr &Ldst);
80 bool noUseOfAddBeforeLoadOrStore(const MachineInstr *Add,
81 const MachineInstr *Ldst);
85 bool canHoistLoadStoreTo(MachineInstr *Ldst, MachineInstr *To);
89 // bool canSinkLoadStoreTo(MachineInstr *Ldst, MachineInstr *To);
95 MachineInstr *canJoinInstruction
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h22 #include "llvm/CodeGen/MachineInstr.h"
66 const MachineInstr &MI, unsigned DefIdx,
79 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
95 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
106 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
113 isCopyInstrImpl(const MachineInstr &MI) const override;
118 describeLoadedValue(const MachineInstr &MI, Register Reg) const override;
128 MachineInstr *convertToThreeAddress(MachineInstr in getSubtarget()
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.h191 void expandRIPseudo(MachineInstr &MI, unsigned LowOpcode, unsigned HighOpcode,
193 void expandRIEPseudo(MachineInstr &MI, unsigned LowOpcode,
195 void expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode,
197 void expandLOCPseudo(MachineInstr &MI, unsigned LowOpcode,
199 void expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
201 void expandLoadStackGuard(MachineInstr *MI) const;
223 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
231 Register isLoadFromStackSlot(const MachineInstr &MI,
233 Register isStoreToStackSlot(const MachineInstr
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/freebsd-src/contrib/llvm-project/llvm/lib/CodeGen/
H A DImplicitNullChecks.cpp81 static bool canHandle(const MachineInstr *MI);
86 bool canReorder(const MachineInstr *A, const MachineInstr *B);
99 std::optional<ArrayRef<MachineInstr *>::iterator> PotentialDependence;
103 std::optional<ArrayRef<MachineInstr *>::iterator> PotentialDependence) in DependenceResult()
115 DependenceResult computeDependence(const MachineInstr *MI,
116 ArrayRef<MachineInstr *> Block);
121 MachineInstr *MemOperation;
124 MachineInstr *CheckOperation;
137 MachineInstr *OnlyDependency;
140 explicit NullCheck(MachineInstr *memOperation, MachineInstr *checkOperation, in NullCheck()
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H A DMachineInstr.cpp1 //===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===//
13 #include "llvm/CodeGen/MachineInstr.h"
65 static const MachineFunction *getMFIfAvailable(const MachineInstr &MI) { in getMFIfAvailable()
74 static void tryToGetTargetInfo(const MachineInstr &MI, in tryToGetTargetInfo()
88 void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) { in addImplicitDefUseOperands()
95 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
98 MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &TID, in MachineInstr()
115 /// MachineInstr cto
97 MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &TID, MachineInstr() function in MachineInstr
117 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI) MachineInstr() function in MachineInstr
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