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Searched refs:uint8_t (Results 1 – 25 of 1875) sorted by relevance

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/dflybsd-src/sys/dev/drm/amd/display/dc/
H A Ddc_dp_types.h110 uint8_t MINOR:4;
111 uint8_t MAJOR:4;
113 uint8_t raw;
118 uint8_t MAX_LANE_COUNT:5;
119 uint8_t POST_LT_ADJ_REQ_SUPPORTED:1;
120 uint8_t TPS3_SUPPORTED:1;
121 uint8_t ENHANCED_FRAME_CAP:1;
123 uint8_t raw;
128 uint8_t MAX_DOWN_SPREAD:1;
129 uint8_t RESERVED:5;
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/dflybsd-src/sys/dev/drm/radeon/
H A Dsmu7_fusion.h46 uint8_t DisplayPhy1Config;
47 uint8_t DisplayPhy2Config;
48 uint8_t DisplayPhy3Config;
49 uint8_t DisplayPhy4Config;
51 uint8_t DisplayPhy5Config;
52 uint8_t DisplayPhy6Config;
53 uint8_t DisplayPhy7Config;
54 uint8_t DisplayPhy8Config;
60 uint8_t SClkDpmEnabledLevels;
61 uint8_t MClkDpmEnabledLevels;
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H A Dsmu7_discrete.h55 uint8_t DisplayPhy1Config;
56 uint8_t DisplayPhy2Config;
57 uint8_t DisplayPhy3Config;
58 uint8_t DisplayPhy4Config;
60 uint8_t DisplayPhy5Config;
61 uint8_t DisplayPhy6Config;
62 uint8_t DisplayPhy7Config;
63 uint8_t DisplayPhy8Config;
69 uint8_t SClkDpmEnabledLevels;
70 uint8_t MClkDpmEnabledLevels;
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/dflybsd-src/sys/dev/drm/amd/powerplay/inc/
H A Dsmu7_fusion.h46 uint8_t DisplayPhy1Config;
47 uint8_t DisplayPhy2Config;
48 uint8_t DisplayPhy3Config;
49 uint8_t DisplayPhy4Config;
51 uint8_t DisplayPhy5Config;
52 uint8_t DisplayPhy6Config;
53 uint8_t DisplayPhy7Config;
54 uint8_t DisplayPhy8Config;
60 uint8_t SClkDpmEnabledLevels;
61 uint8_t MClkDpmEnabledLevels;
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H A Dsmu74_discrete.h44 uint8_t vco_setting;
45 uint8_t postdiv;
55 uint8_t Smio;
56 uint8_t padding;
72 uint8_t PllRange;
73 uint8_t SSc_En;
85 uint8_t pcieDpmLevel;
86 uint8_t DeepSleepDivId;
92 uint8_t SclkDid;
93 uint8_t padding;
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H A Dsmu73_discrete.h33 uint8_t Smio;
34 uint8_t padding;
51 uint8_t pcieDpmLevel;
52 uint8_t DeepSleepDivId;
60 uint8_t SclkDid;
61 uint8_t DisplayWatermark;
62 uint8_t EnabledForActivity;
63 uint8_t EnabledForThrottle;
64 uint8_t UpHyst;
65 uint8_t DownHyst;
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H A Dsmu75_discrete.h43 uint8_t vco_setting; /* 1: 3-6GHz, 3: 2-4GHz */
44 uint8_t postdiv; /* divide by 2^n */
53 uint8_t Smio;
54 uint8_t padding;
70 uint8_t PllRange;
71 uint8_t SSc_En;
84 uint8_t pcieDpmLevel;
85 uint8_t DeepSleepDivId;
93 uint8_t SclkDid;
94 uint8_t padding;
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H A Dsmu71_discrete.h41 uint8_t Smio;
42 uint8_t padding;
54 uint8_t pcieDpmLevel;
55 uint8_t DeepSleepDivId;
64 uint8_t SclkDid;
65 uint8_t DisplayWatermark;
66 uint8_t EnabledForActivity;
67 uint8_t EnabledForThrottle;
68 uint8_t UpHyst;
69 uint8_t DownHyst;
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H A Dsmu7_discrete.h55 uint8_t DisplayPhy1Config;
56 uint8_t DisplayPhy2Config;
57 uint8_t DisplayPhy3Config;
58 uint8_t DisplayPhy4Config;
60 uint8_t DisplayPhy5Config;
61 uint8_t DisplayPhy6Config;
62 uint8_t DisplayPhy7Config;
63 uint8_t DisplayPhy8Config;
69 uint8_t SClkDpmEnabledLevels;
70 uint8_t MClkDpmEnabledLevels;
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H A Dsmu72_discrete.h35 uint8_t Smio;
36 uint8_t padding;
52 uint8_t pcieDpmLevel;
53 uint8_t DeepSleepDivId;
62 uint8_t SclkDid;
63 uint8_t DisplayWatermark;
64 uint8_t EnabledForActivity;
65 uint8_t EnabledForThrottle;
66 uint8_t UpHyst;
67 uint8_t DownHyst;
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H A Dsmu9_driver_if.h84 uint8_t SsOn;
85 uint8_t Did; /* DID */
93 uint8_t a0_shift;
94 uint8_t a1_shift;
95 uint8_t a2_shift;
96 uint8_t padding;
104 uint8_t m1_shift;
105 uint8_t m2_shift;
106 uint8_t b_shift;
107 uint8_t padding;
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H A Dsmu71.h150 uint8_t TdpClampMode;
151 uint8_t TdcClampMode;
152 uint8_t ThermClampMode;
153 uint8_t VoltageBusy;
157 uint8_t LevelChangeInProgress;
158 uint8_t UpHyst;
160 uint8_t DownHyst;
161 uint8_t VoltageDownHyst;
162 uint8_t DpmEnable;
163 uint8_t DpmRunning;
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H A Dsmu72.h54 uint8_t a_shift;
55 uint8_t b_shift;
56 uint8_t c_shift;
57 uint8_t x_shift;
82 uint8_t index;
197 uint8_t waterfall_up;
198 uint8_t waterfall_down;
199 uint8_t waterfall_limit;
200 uint8_t spare;
234 uint8_t TdpClampMode;
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/dflybsd-src/contrib/libpcap/
H A Dextract.h243 ((uint16_t)(((uint16_t)(*((const uint8_t *)(p) + 0)) << 8) | \
244 ((uint16_t)(*((const uint8_t *)(p) + 1)) << 0)))
246 ((int16_t)(((uint16_t)(*((const uint8_t *)(p) + 0)) << 8) | \
247 ((uint16_t)(*((const uint8_t *)(p) + 1)) << 0)))
249 ((uint32_t)(((uint32_t)(*((const uint8_t *)(p) + 0)) << 24) | \
250 ((uint32_t)(*((const uint8_t *)(p) + 1)) << 16) | \
251 ((uint32_t)(*((const uint8_t *)(p) + 2)) << 8) | \
252 ((uint32_t)(*((const uint8_t *)(p) + 3)) << 0)))
254 ((int32_t)(((uint32_t)(*((const uint8_t *)(p) + 0)) << 24) | \
255 ((uint32_t)(*((const uint8_t *)(p) + 1)) << 16) | \
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/dflybsd-src/sys/dev/drm/amd/include/
H A Datomfirmware.h52 #ifndef uint8_t
53 typedef unsigned char uint8_t; typedef
227 …uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compa…
228 …uint8_t content_revision; //change it when a data table has a structure change, or a hw function…
237 …uint8_t atom_bios_string[4]; //enum atom_string_def atom_bios_string; //Signature to d…
440 uint8_t h_border;
441 uint8_t v_border;
443 uint8_t atom_mode_id;
444 uint8_t refreshrate;
483 uint8_t mem_module_id;
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/dflybsd-src/sys/netproto/802_11/
H A Dieee80211_mesh.h46 uint8_t conf_ie; /* IEEE80211_ELEMID_MESHCONF */
47 uint8_t conf_len;
48 uint8_t conf_pselid; /* Active Path Sel. Proto. ID */
49 uint8_t conf_pmetid; /* Active Metric Identifier */
50 uint8_t conf_ccid; /* Congestion Control Mode ID */
51 uint8_t conf_syncid; /* Sync. Protocol ID */
52 uint8_t conf_authid; /* Auth. Protocol ID */
53 uint8_t conf_form; /* Formation Information */
54 uint8_t conf_cap;
117 uint8_t id_ie; /* IEEE80211_ELEMID_MESHID */
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H A Dieee80211.h40 extern const uint8_t ieee80211broadcastaddr[];
48 uint8_t i_signal;
49 uint8_t i_service;
66 uint8_t i_fc[2];
67 uint8_t i_dur[2];
68 uint8_t i_addr1[IEEE80211_ADDR_LEN];
69 uint8_t i_addr2[IEEE80211_ADDR_LEN];
70 uint8_t i_addr3[IEEE80211_ADDR_LEN];
71 uint8_t i_seq[2];
77 uint8_t i_fc[2];
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/dflybsd-src/usr.sbin/fstyp/
H A Dmsdosfs.h55 uint8_t BS_jmpBoot[3];
56 uint8_t BS_OEMName[8];
57 uint8_t BPB_BytsPerSec[2];
58 uint8_t BPB_SecPerClus;
59 uint8_t BPB_RsvdSecCnt[2];
60 uint8_t BPB_NumFATs;
61 uint8_t BPB_RootEntCnt[2];
62 uint8_t BPB_TotSec16[2];
63 uint8_t BPB_Media;
64 uint8_t BPB_FATSz16[2];
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/dflybsd-src/sys/dev/netif/ath/ath_hal/
H A Dah_eeprom_v14.h122 uint8_t spurRangeLow;
123 uint8_t spurRangeHigh;
127 uint8_t bChannel;
128 uint8_t tPow2x[4];
132 uint8_t bChannel;
133 uint8_t tPow2x[8];
137 uint8_t bChannel;
138 uint8_t tPowerFlag; /* [0..5] tPower [6..7] flag */
167 uint8_t opCapFlags;
168 uint8_t eepMisc;
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H A Dah_eeprom_v4k.h64 uint8_t opCapFlags;
65 uint8_t eepMisc;
67 uint8_t macAddr[6];
68 uint8_t rxMask;
69 uint8_t txMask;
74 uint8_t deviceType;
75 uint8_t txGainType; /* high power tx gain table support */
82 uint8_t switchSettling; // 1
83 uint8_t txRxAttenCh[AR5416_4K_MAX_CHAINS]; // 1
84 uint8_t rxTxMarginCh[AR5416_4K_MAX_CHAINS]; // 1
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/dflybsd-src/sys/dev/drm/amd/powerplay/hwmgr/
H A Dppatomfwctrl.h47 uint8_t psi0_enable;
48 uint8_t psi1_enable;
49 uint8_t max_vid_step;
50 uint8_t telemetry_offset;
51 uint8_t telemetry_slope;
57 uint8_t uc_gpio_pin_bit_shift;
66 uint8_t ucPll_ss_enable;
67 uint8_t ucReserve;
96 uint8_t ucEnableGbVdroopTableCkson;
97 uint8_t ucEnableGbFuseTableCkson;
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/dflybsd-src/sys/dev/raid/mfi/
H A Dmfireg.h495 uint8_t cmd;
496 uint8_t sense_len;
497 uint8_t cmd_status;
498 uint8_t scsi_status;
499 uint8_t target_id;
500 uint8_t lun_id;
501 uint8_t cdb_len;
502 uint8_t sg_count;
560 uint8_t cdb[16];
568 uint8_t mbox[MFI_MBOX_SIZE];
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/dflybsd-src/sys/dev/netif/iwi/
H A Dif_iwireg.h169 uint8_t type;
175 uint8_t seq;
176 uint8_t flags;
179 uint8_t reserved;
184 uint8_t type;
198 uint8_t flags;
204 uint8_t state;
215 uint8_t state;
218 uint8_t pad[11];
223 uint8_t nchan;
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/dflybsd-src/sys/netbt/
H A Dhci.h407 uint8_t type; /* MUST be 0x01 */
409 uint8_t length; /* parameter(s) length in bytes */
417 uint8_t type; /* MUST be 0x02 */
427 uint8_t type; /* MUST be 0x03 */
429 uint8_t length; /* payload length in bytes */
437 uint8_t type; /* MUST be 0x04 */
438 uint8_t event; /* event */
439 uint8_t length; /* parameter(s) length in bytes */
447 uint8_t status; /* 0x00 - success */
461 uint8_t lap[HCI_LAP_SIZE]; /* LAP */
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/dflybsd-src/contrib/tcpdump/
H A Dextract.h31 #define EXTRACT_U_1(p) ((uint8_t)(*(p)))
274 ((uint16_t)(((uint16_t)(*((const uint8_t *)(p) + 0)) << 8) | \
275 ((uint16_t)(*((const uint8_t *)(p) + 1)) << 0)))
277 ((int16_t)(((uint16_t)(*((const uint8_t *)(p) + 0)) << 8) | \
278 ((uint16_t)(*((const uint8_t *)(p) + 1)) << 0)))
280 ((uint32_t)(((uint32_t)(*((const uint8_t *)(p) + 0)) << 24) | \
281 ((uint32_t)(*((const uint8_t *)(p) + 1)) << 16) | \
282 ((uint32_t)(*((const uint8_t *)(p) + 2)) << 8) | \
283 ((uint32_t)(*((const uint8_t *)(p) + 3)) << 0)))
285 ((int32_t)(((uint32_t)(*((const uint8_t *)(p) + 0)) << 24) | \
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