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Searched refs:simulated (Results 1 – 14 of 14) sorted by relevance

/dflybsd-src/test/interbench/
H A Dreadme29 threads of the simulated interactive tasks and then measures the latency in the
32 considered as the time from this sleep till the simulated task gets scheduled.
38 What interactive tasks are simulated and how?
41 X is simulated as a thread that uses a variable amount of cpu ranging from 0 to
46 Audio is simulated as a thread that tries to run at 50ms intervals that then
54 Video is simulated as a thread that tries to receive cpu 60 times per second
73 What loads are simulated?
128 --- Benchmarking simulated cpu of X in the presence of simulated ---
/dflybsd-src/sys/contrib/dev/acpica/generate/unix/
H A Dreadme.txt83 the AML interpreter. Hardware access is simulated.
/dflybsd-src/etc/etc.x86_64/
H A Ddisktab7 # ty type of disk (fixed, removeable, simulated)
/dflybsd-src/games/larn/
H A DFixed.Bugs126 delete line codes, and the scrolling region must be simulated with vertical
/dflybsd-src/contrib/file/magic/Magdir/
H A Dmacintosh231 >0 string CIRC simulated circuit
/dflybsd-src/contrib/wpa_supplicant/wpa_supplicant/
H A DREADME-HS20351 Add a SIM credential using a simulated SIM/USIM card for testing:
/dflybsd-src/contrib/gcc-4.7/gcc/
H A Dtarget.def598 change the pipeline hazard recognizer state when the new simulated
603 new simulated processor cycle correspondingly starts and finishes. */
/dflybsd-src/contrib/gcc-8.0/gcc/
H A Dtarget.def995 constraint to issue insns on the same simulated processor cycle (see\n\
1123 change the pipeline hazard recognizer state when the new simulated
1128 new simulated processor cycle correspondingly starts and finishes. */
1139 when the new simulated processor cycle starts. Usage of the hook may\n\
1143 when the new simulated processor cycle starts.",
1156 simulated processor cycle finishes.",
1166 "The hook to notify target that the current simulated cycle is about to finish.\n\
1174 "The hook to notify target that new simulated cycle has just started.\n\
/dflybsd-src/sys/dev/drm/i915/
H A Di915_drv.h904 bool simulated; member
/dflybsd-src/contrib/gcc-4.7/gcc/doc/
H A Dtm.texi6517 constraint to issue insns on the same simulated processor cycle (see
6634 when the new simulated processor cycle starts. Usage of the hook may
6638 when the new simulated processor cycle starts.
6648 simulated processor cycle finishes.
6657 The hook to notify target that the current simulated cycle is about to finish.
6664 The hook to notify target that new simulated cycle has just started.
H A Dtm.texi.in6439 constraint to issue insns on the same simulated processor cycle (see
6556 when the new simulated processor cycle starts. Usage of the hook may
6560 when the new simulated processor cycle starts.
6570 simulated processor cycle finishes.
6579 The hook to notify target that the current simulated cycle is about to finish.
6586 The hook to notify target that new simulated cycle has just started.
H A Dmd.texi8157 on a given simulated processor cycle. The pipeline hazard recognizer is
/dflybsd-src/contrib/ncurses/misc/
H A Dterminfo.src19654 # Bold, dim, and standout are simulated by colors and thus not allowed
23228 # 1. underlining is not allowed with colors: first, is is simulated by
23285 # it's simulated with cyan
/dflybsd-src/sys/contrib/dev/acpica/
H A Dchanges.txt10524 actual Switch opcode, it must be simulated with local named temporary