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Searched refs:reg_offset (Results 1 – 25 of 35) sorted by relevance

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/dflybsd-src/sys/dev/drm/amd/amdgpu/
H A Dvega10_reg_init.c35 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega10_reg_base_init()
36 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in vega10_reg_base_init()
37 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in vega10_reg_base_init()
38 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); in vega10_reg_base_init()
39 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in vega10_reg_base_init()
40 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in vega10_reg_base_init()
41 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in vega10_reg_base_init()
42 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); in vega10_reg_base_init()
43 adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i])); in vega10_reg_base_init()
44 adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i])); in vega10_reg_base_init()
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H A Dvega20_reg_init.c35 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega20_reg_base_init()
36 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in vega20_reg_base_init()
37 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in vega20_reg_base_init()
38 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); in vega20_reg_base_init()
39 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in vega20_reg_base_init()
40 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in vega20_reg_base_init()
41 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in vega20_reg_base_init()
42 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); in vega20_reg_base_init()
43 adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i])); in vega20_reg_base_init()
44 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); in vega20_reg_base_init()
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H A Dmmsch_v1_0.h51 uint32_t reg_offset : 28; member
56 uint32_t reg_offset : 20; member
89 uint32_t reg_offset, in mmsch_v1_0_insert_direct_wt() argument
92 direct_wt->cmd_header.reg_offset = reg_offset; in mmsch_v1_0_insert_direct_wt()
99 uint32_t reg_offset, in mmsch_v1_0_insert_direct_rd_mod_wt() argument
102 direct_rd_mod_wt->cmd_header.reg_offset = reg_offset; in mmsch_v1_0_insert_direct_rd_mod_wt()
111 uint32_t reg_offset, in mmsch_v1_0_insert_direct_poll() argument
114 direct_poll->cmd_header.reg_offset = reg_offset; in mmsch_v1_0_insert_direct_poll()
H A Dsoc15_common.h28 #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
31 WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
32 (RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \
36 RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
39 RREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset)
42 WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
45 WREG32_NO_KIQ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
48 WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value)
52 uint32_t tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
57 tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
H A Dvcn_v1_0.c1405 uint32_t reg_offset = (reg << 2); in vcn_v1_0_jpeg_ring_emit_reg_wait() local
1417 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || in vcn_v1_0_jpeg_ring_emit_reg_wait()
1418 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { in vcn_v1_0_jpeg_ring_emit_reg_wait()
1421 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3)); in vcn_v1_0_jpeg_ring_emit_reg_wait()
1423 amdgpu_ring_write(ring, reg_offset); in vcn_v1_0_jpeg_ring_emit_reg_wait()
1449 uint32_t reg_offset = (reg << 2); in vcn_v1_0_jpeg_ring_emit_wreg() local
1453 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || in vcn_v1_0_jpeg_ring_emit_wreg()
1454 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { in vcn_v1_0_jpeg_ring_emit_wreg()
1457 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0)); in vcn_v1_0_jpeg_ring_emit_wreg()
1459 amdgpu_ring_write(ring, reg_offset); in vcn_v1_0_jpeg_ring_emit_wreg()
[all …]
H A Dsoc15.c270 uint32_t reg_offset; member
298 u32 sh_num, u32 reg_offset) in soc15_read_indexed_register() argument
306 val = RREG32(reg_offset); in soc15_read_indexed_register()
316 u32 sh_num, u32 reg_offset) in soc15_get_register_value() argument
319 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc15_get_register_value()
321 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) in soc15_get_register_value()
323 else if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2)) in soc15_get_register_value()
325 return RREG32(reg_offset); in soc15_get_register_value()
330 u32 sh_num, u32 reg_offset, u32 *value) in soc15_read_register() argument
338 if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] in soc15_read_register()
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H A Dgfx_v8_0.c2231 u32 reg_offset; in gfx_v8_0_tiling_mode_table_init() local
2236 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
2237 modearray[reg_offset] = 0; in gfx_v8_0_tiling_mode_table_init()
2239 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
2240 mod2array[reg_offset] = 0; in gfx_v8_0_tiling_mode_table_init()
2404 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
2405 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 && in gfx_v8_0_tiling_mode_table_init()
2406 reg_offset != 23) in gfx_v8_0_tiling_mode_table_init()
2407 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
2409 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
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H A Dvi.c552 u32 sh_num, u32 reg_offset) in vi_get_register_value() argument
559 switch (reg_offset) { in vi_get_register_value()
574 val = RREG32(reg_offset); in vi_get_register_value()
583 switch (reg_offset) { in vi_get_register_value()
620 idx = (reg_offset - mmGB_TILE_MODE0); in vi_get_register_value()
638 idx = (reg_offset - mmGB_MACROTILE_MODE0); in vi_get_register_value()
641 return RREG32(reg_offset); in vi_get_register_value()
647 u32 sh_num, u32 reg_offset, u32 *value) in vi_read_register() argument
655 if (reg_offset != vi_allowed_read_registers[i].reg_offset) in vi_read_register()
659 reg_offset); in vi_read_register()
H A Dcik.c1028 u32 sh_num, u32 reg_offset) in cik_get_register_value() argument
1035 switch (reg_offset) { in cik_get_register_value()
1050 val = RREG32(reg_offset); in cik_get_register_value()
1059 switch (reg_offset) { in cik_get_register_value()
1096 idx = (reg_offset - mmGB_TILE_MODE0); in cik_get_register_value()
1114 idx = (reg_offset - mmGB_MACROTILE_MODE0); in cik_get_register_value()
1117 return RREG32(reg_offset); in cik_get_register_value()
1123 u32 sh_num, u32 reg_offset, u32 *value) in cik_read_register() argument
1131 if (reg_offset != cik_allowed_read_registers[i].reg_offset) in cik_read_register()
1135 reg_offset); in cik_read_register()
H A Dsdma_v4_0.c150 return ( 0 == instance ? (adev->reg_offset[SDMA0_HWIP][0][0] + offset) : in sdma_v4_0_get_reg_offset()
151 (adev->reg_offset[SDMA1_HWIP][0][0] + offset)); in sdma_v4_0_get_reg_offset()
1378 u32 reg_offset = (type == AMDGPU_SDMA_IRQ_TRAP0) ? in sdma_v4_0_set_trap_irq_state() local
1382 sdma_cntl = RREG32(reg_offset); in sdma_v4_0_set_trap_irq_state()
1385 WREG32(reg_offset, sdma_cntl); in sdma_v4_0_set_trap_irq_state()
H A Damdgpu_amdkfd_gfx_v8.c93 unsigned int reg_offset);
763 unsigned int reg_offset) in kgd_address_watch_get_offset() argument
H A Damdgpu_amdkfd_gfx_v9.c134 unsigned int reg_offset);
949 unsigned int reg_offset) in kgd_address_watch_get_offset() argument
/dflybsd-src/sys/dev/drm/radeon/
H A Dcik_sdma.c250 u32 rb_cntl, reg_offset; in cik_sdma_gfx_stop() local
259 reg_offset = SDMA0_REGISTER_OFFSET; in cik_sdma_gfx_stop()
261 reg_offset = SDMA1_REGISTER_OFFSET; in cik_sdma_gfx_stop()
262 rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset); in cik_sdma_gfx_stop()
264 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); in cik_sdma_gfx_stop()
265 WREG32(SDMA0_GFX_IB_CNTL + reg_offset, 0); in cik_sdma_gfx_stop()
304 uint32_t reg_offset, value; in cik_sdma_ctx_switch_enable() local
309 reg_offset = SDMA0_REGISTER_OFFSET; in cik_sdma_ctx_switch_enable()
311 reg_offset = SDMA1_REGISTER_OFFSET; in cik_sdma_ctx_switch_enable()
312 value = RREG32(SDMA0_CNTL + reg_offset); in cik_sdma_ctx_switch_enable()
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H A Dni_dma.c190 u32 reg_offset, wb_offset; in cayman_dma_resume() local
196 reg_offset = DMA0_REGISTER_OFFSET; in cayman_dma_resume()
200 reg_offset = DMA1_REGISTER_OFFSET; in cayman_dma_resume()
204 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0); in cayman_dma_resume()
205 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0); in cayman_dma_resume()
213 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl); in cayman_dma_resume()
216 WREG32(DMA_RB_RPTR + reg_offset, 0); in cayman_dma_resume()
217 WREG32(DMA_RB_WPTR + reg_offset, 0); in cayman_dma_resume()
220 WREG32(DMA_RB_RPTR_ADDR_HI + reg_offset, in cayman_dma_resume()
222 WREG32(DMA_RB_RPTR_ADDR_LO + reg_offset, in cayman_dma_resume()
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H A Dcik.c2356 u32 reg_offset, split_equal_to_row_size; in cik_tiling_mode_table_init() local
2378 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in cik_tiling_mode_table_init()
2379 tile[reg_offset] = 0; in cik_tiling_mode_table_init()
2380 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) in cik_tiling_mode_table_init()
2381 macrotile[reg_offset] = 0; in cik_tiling_mode_table_init()
2521 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in cik_tiling_mode_table_init()
2522 WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]); in cik_tiling_mode_table_init()
2523 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) in cik_tiling_mode_table_init()
2524 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]); in cik_tiling_mode_table_init()
2664 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in cik_tiling_mode_table_init()
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H A Dsi.c2484 u32 reg_offset, split_equal_to_row_size; in si_tiling_mode_table_init() local
2499 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in si_tiling_mode_table_init()
2500 tile[reg_offset] = 0; in si_tiling_mode_table_init()
2713 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in si_tiling_mode_table_init()
2714 WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]); in si_tiling_mode_table_init()
2928 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in si_tiling_mode_table_init()
2929 WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]); in si_tiling_mode_table_init()
H A Drv770_dpm.h282 u16 reg_offset, u32 value);
/dflybsd-src/contrib/gdb-7/gdb/
H A Damd64-nat.c57 int *reg_offset = amd64_native_gregset64_reg_offset; in amd64_native_gregset_reg_offset() local
64 reg_offset = amd64_native_gregset32_reg_offset; in amd64_native_gregset_reg_offset()
72 return reg_offset[regnum]; in amd64_native_gregset_reg_offset()
H A Dfindvar.c687 int reg_offset = value_offset (value); in read_frame_register_value() local
694 while (reg_offset >= register_size (gdbarch, regnum)) in read_frame_register_value()
696 reg_offset -= register_size (gdbarch, regnum); in read_frame_register_value()
704 int reg_len = TYPE_LENGTH (value_type (regval)) - reg_offset; in read_frame_register_value()
717 value_contents_copy (value, offset, regval, reg_offset, reg_len); in read_frame_register_value()
721 reg_offset = 0; in read_frame_register_value()
H A Ddwarf2loc.c1629 int reg_offset = source_offset; in read_pieced_value() local
1635 reg_offset = register_size (arch, gdb_regnum) - this_size; in read_pieced_value()
1645 if (!get_frame_register_bytes (frame, gdb_regnum, reg_offset, in read_pieced_value()
1821 int reg_offset = dest_offset; in write_pieced_value() local
1826 reg_offset = register_size (arch, gdb_regnum) - this_size; in write_pieced_value()
1834 if (!get_frame_register_bytes (frame, gdb_regnum, reg_offset, in write_pieced_value()
1854 put_frame_register_bytes (frame, gdb_regnum, reg_offset, in write_pieced_value()
/dflybsd-src/contrib/gcc-4.7/gcc/
H A Dpostreload.c1640 static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER]; variable
1674 rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[regno], in move2add_use_add2_insn()
1691 if (INTVAL (off) == reg_offset [regno]) in move2add_use_add2_insn()
1716 && ((reg_offset[regno] & ~GET_MODE_MASK (narrow_mode)) in move2add_use_add2_insn()
1740 reg_offset[regno] = INTVAL (off); in move2add_use_add2_insn()
1780 rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[i], in move2add_use_add3_insn()
1815 rtx new_src = gen_int_mode (INTVAL (off) - reg_offset[min_regno], in move2add_use_add3_insn()
1826 reg_offset[regno] = INTVAL (off); in move2add_use_add3_insn()
1842 reg_offset[i] = 0; in reload_cse_move2add()
1930 HOST_WIDE_INT base_offset = reg_offset[REGNO (src)]; in reload_cse_move2add()
[all …]
/dflybsd-src/contrib/gcc-8.0/gcc/
H A Dpostreload.c1631 static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER]; variable
1688 reg_offset[regno] = INTVAL (off); in move2add_record_sym_value()
1739 rtx new_src = gen_int_mode (UINTVAL (off) - reg_offset[regno], mode); in move2add_use_add2_insn()
1755 if (INTVAL (off) == reg_offset [regno]) in move2add_use_add2_insn()
1777 && ((reg_offset[regno] & ~GET_MODE_MASK (narrow_mode)) in move2add_use_add2_insn()
1839 rtx new_src = gen_int_mode (UINTVAL (off) - reg_offset[i], in move2add_use_add3_insn()
1874 rtx new_src = gen_int_mode (UINTVAL (off) - reg_offset[min_regno], in move2add_use_add3_insn()
1898 reg_offset[i] = 0; in reload_cse_move2add()
1987 HOST_WIDE_INT base_offset = reg_offset[REGNO (src)]; in reload_cse_move2add()
1988 HOST_WIDE_INT regno_offset = reg_offset[regno]; in reload_cse_move2add()
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/dflybsd-src/sys/dev/netif/ix/
H A Dixgbe_mbx.c597 u32 reg_offset = (vf_number < 32) ? 0 : 1; in ixgbe_check_for_rst_pf() local
606 vflre = IXGBE_READ_REG(hw, IXGBE_VFLRE(reg_offset)); in ixgbe_check_for_rst_pf()
612 vflre = IXGBE_READ_REG(hw, IXGBE_VFLREC(reg_offset)); in ixgbe_check_for_rst_pf()
620 IXGBE_WRITE_REG(hw, IXGBE_VFLREC(reg_offset), (1 << vf_shift)); in ixgbe_check_for_rst_pf()
/dflybsd-src/sys/dev/drm/amd/include/
H A Dkgd_kfd_interface.h357 unsigned int reg_offset);
/dflybsd-src/sys/dev/netif/ig_hal/
H A De1000_82575.c2276 u32 reg_val, reg_offset; in e1000_vmdq_set_anti_spoofing_pf() local
2280 reg_offset = E1000_DTXSWC; in e1000_vmdq_set_anti_spoofing_pf()
2284 reg_offset = E1000_TXSWC; in e1000_vmdq_set_anti_spoofing_pf()
2290 reg_val = E1000_READ_REG(hw, reg_offset); in e1000_vmdq_set_anti_spoofing_pf()
2302 E1000_WRITE_REG(hw, reg_offset, reg_val); in e1000_vmdq_set_anti_spoofing_pf()

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