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Searched refs:pipe (Results 1 – 25 of 290) sorted by relevance

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/dflybsd-src/sys/dev/drm/
H A Ddrm_vblank.c80 drm_get_last_vbltimestamp(struct drm_device *dev, unsigned int pipe,
92 static void store_vblank(struct drm_device *dev, unsigned int pipe, in store_vblank() argument
96 struct drm_vblank_crtc *vblank = &dev->vblank[pipe]; in store_vblank()
112 static u32 drm_vblank_no_hw_counter(struct drm_device *dev, unsigned int pipe) in drm_vblank_no_hw_counter() argument
118 static u32 __get_vblank_counter(struct drm_device *dev, unsigned int pipe) in __get_vblank_counter() argument
121 struct drm_crtc *crtc = drm_crtc_from_index(dev, pipe); in __get_vblank_counter()
128 return dev->driver->get_vblank_counter(dev, pipe); in __get_vblank_counter()
130 return drm_vblank_no_hw_counter(dev, pipe); in __get_vblank_counter()
142 static void drm_reset_vblank_timestamp(struct drm_device *dev, unsigned int pipe) in drm_reset_vblank_timestamp() argument
156 cur_vblank = __get_vblank_counter(dev, pipe); in drm_reset_vblank_timestamp()
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H A Ddrm_simple_kms_helper.c53 struct drm_simple_display_pipe *pipe; in drm_simple_kms_crtc_enable() local
55 pipe = container_of(crtc, struct drm_simple_display_pipe, crtc); in drm_simple_kms_crtc_enable()
56 if (!pipe->funcs || !pipe->funcs->enable) in drm_simple_kms_crtc_enable()
59 pipe->funcs->enable(pipe, crtc->state); in drm_simple_kms_crtc_enable()
65 struct drm_simple_display_pipe *pipe; in drm_simple_kms_crtc_disable() local
67 pipe = container_of(crtc, struct drm_simple_display_pipe, crtc); in drm_simple_kms_crtc_disable()
68 if (!pipe->funcs || !pipe->funcs->disable) in drm_simple_kms_crtc_disable()
71 pipe->funcs->disable(pipe); in drm_simple_kms_crtc_disable()
93 struct drm_simple_display_pipe *pipe; in drm_simple_kms_plane_atomic_check() local
97 pipe = container_of(plane, struct drm_simple_display_pipe, plane); in drm_simple_kms_plane_atomic_check()
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/dflybsd-src/sys/kern/
H A Dsys_pipe.c116 SYSCTL_NODE(_kern, OID_AUTO, pipe, CTLFLAG_RW, 0, "Pipe operation");
179 static void pipeclose (struct pipe *pipe,
182 static int pipe_create (struct pipe **pipep);
280 struct pipe *pipe; in kern_pipe() local
283 pipe = NULL; in kern_pipe()
284 if (pipe_create(&pipe)) { in kern_pipe()
285 pipeclose(pipe, &pipe->bufferA, &pipe->bufferB); in kern_pipe()
286 pipeclose(pipe, &pipe->bufferB, &pipe->bufferA); in kern_pipe()
292 pipeclose(pipe, &pipe->bufferA, &pipe->bufferB); in kern_pipe()
293 pipeclose(pipe, &pipe->bufferB, &pipe->bufferA); in kern_pipe()
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/dflybsd-src/sys/dev/drm/i915/
H A Dintel_color.c112 int pipe = intel_crtc->pipe; in i9xx_load_ycbcr_conversion_matrix() local
115 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); in i9xx_load_ycbcr_conversion_matrix()
116 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); in i9xx_load_ycbcr_conversion_matrix()
117 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); in i9xx_load_ycbcr_conversion_matrix()
119 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), CSC_RGB_TO_YUV_RU_GU); in i9xx_load_ycbcr_conversion_matrix()
120 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), CSC_RGB_TO_YUV_BU); in i9xx_load_ycbcr_conversion_matrix()
122 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), CSC_RGB_TO_YUV_RY_GY); in i9xx_load_ycbcr_conversion_matrix()
123 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), CSC_RGB_TO_YUV_BY); in i9xx_load_ycbcr_conversion_matrix()
125 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), CSC_RGB_TO_YUV_RV_GV); in i9xx_load_ycbcr_conversion_matrix()
126 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), CSC_RGB_TO_YUV_BV); in i9xx_load_ycbcr_conversion_matrix()
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H A Dintel_fifo_underrun.c55 enum i915_pipe pipe; in ivb_can_enable_err_int() local
59 for_each_pipe(dev_priv, pipe) { in ivb_can_enable_err_int()
60 crtc = intel_get_crtc_for_pipe(dev_priv, pipe); in ivb_can_enable_err_int()
72 enum i915_pipe pipe; in cpt_can_enable_serr_int() local
77 for_each_pipe(dev_priv, pipe) { in cpt_can_enable_serr_int()
78 crtc = intel_get_crtc_for_pipe(dev_priv, pipe); in cpt_can_enable_serr_int()
90 i915_reg_t reg = PIPESTAT(crtc->pipe); in i9xx_check_fifo_underruns()
98 enable_mask = i915_pipestat_enable_mask(dev_priv, crtc->pipe); in i9xx_check_fifo_underruns()
102 trace_intel_cpu_fifo_underrun(dev_priv, crtc->pipe); in i9xx_check_fifo_underruns()
103 DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe)); in i9xx_check_fifo_underruns()
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H A Dintel_dpio_phy.c647 enum i915_pipe pipe = intel_crtc->pipe; in chv_set_phy_signal_level() local
654 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); in chv_set_phy_signal_level()
658 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); in chv_set_phy_signal_level()
661 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); in chv_set_phy_signal_level()
665 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); in chv_set_phy_signal_level()
668 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); in chv_set_phy_signal_level()
671 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); in chv_set_phy_signal_level()
674 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); in chv_set_phy_signal_level()
677 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); in chv_set_phy_signal_level()
682 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); in chv_set_phy_signal_level()
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H A Di915_reg.h144 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) argument
145 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) argument
152 #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) argument
153 #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) argument
1155 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL) argument
1208 #define _DP_SSC(val, pipe) ((val) << (2 * (pipe))) argument
1209 #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe)) argument
1210 #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe)) argument
1211 #define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe)) argument
1212 #define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe)) argument
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H A Dintel_sprite.c136 pipe_name(crtc->pipe)); in intel_pipe_update_start()
187 enum i915_pipe pipe = crtc->pipe; in intel_pipe_update_end() local
217 pipe_name(pipe), crtc->debug.start_vbl_count, in intel_pipe_update_end()
227 pipe_name(pipe), in intel_pipe_update_end()
241 enum i915_pipe pipe = plane->pipe; in skl_update_plane() local
267 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id), in skl_update_plane()
274 I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value); in skl_update_plane()
275 I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), key->max_value); in skl_update_plane()
276 I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), key->channel_mask); in skl_update_plane()
279 I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x); in skl_update_plane()
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H A Dintel_audio.c289 enum i915_pipe pipe = intel_crtc->pipe; in hsw_dp_audio_config_update() local
297 tmp = I915_READ(HSW_AUD_CFG(pipe)); in hsw_dp_audio_config_update()
309 I915_WRITE(HSW_AUD_CFG(pipe), tmp); in hsw_dp_audio_config_update()
311 tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(pipe)); in hsw_dp_audio_config_update()
322 I915_WRITE(HSW_AUD_M_CTS_ENABLE(pipe), tmp); in hsw_dp_audio_config_update()
332 enum i915_pipe pipe = intel_crtc->pipe; in hsw_hdmi_audio_config_update() local
336 tmp = I915_READ(HSW_AUD_CFG(pipe)); in hsw_hdmi_audio_config_update()
353 I915_WRITE(HSW_AUD_CFG(pipe), tmp); in hsw_hdmi_audio_config_update()
359 tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(pipe)); in hsw_hdmi_audio_config_update()
362 I915_WRITE(HSW_AUD_M_CTS_ENABLE(pipe), tmp); in hsw_hdmi_audio_config_update()
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H A Di915_irq.c525 enum i915_pipe pipe, in bdw_update_pipe_irq() argument
538 new_val = dev_priv->de_irq_mask[pipe]; in bdw_update_pipe_irq()
542 if (new_val != dev_priv->de_irq_mask[pipe]) { in bdw_update_pipe_irq()
543 dev_priv->de_irq_mask[pipe] = new_val; in bdw_update_pipe_irq()
544 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); in bdw_update_pipe_irq()
545 POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); in bdw_update_pipe_irq()
575 enum i915_pipe pipe) in i915_pipestat_enable_mask() argument
577 u32 status_mask = dev_priv->pipestat_irq_mask[pipe]; in i915_pipestat_enable_mask()
610 pipe_name(pipe), enable_mask, status_mask); in i915_pipestat_enable_mask()
616 enum i915_pipe pipe, u32 status_mask) in i915_enable_pipestat() argument
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H A Dintel_display.c996 enum i915_pipe pipe) in intel_pipe_to_cpu_transcoder() argument
998 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); in intel_pipe_to_cpu_transcoder()
1004 enum i915_pipe pipe) in pipe_scanline_is_moving() argument
1006 i915_reg_t reg = PIPEDSL(pipe); in pipe_scanline_is_moving()
1025 enum i915_pipe pipe = crtc->pipe; in wait_for_pipe_scanline_moving() local
1028 if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100)) in wait_for_pipe_scanline_moving()
1030 pipe_name(pipe), onoff(state)); in wait_for_pipe_scanline_moving()
1079 enum i915_pipe pipe, bool state) in assert_pll() argument
1084 val = I915_READ(DPLL(pipe)); in assert_pll()
1108 enum i915_pipe pipe, bool state) in assert_fdi_tx() argument
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H A Dintel_psr.c67 static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe) in vlv_is_psr_active_on_pipe() argument
72 val = I915_READ(VLV_PSRSTAT(pipe)) & in vlv_is_psr_active_on_pipe()
86 val = I915_READ(VLV_VSCSDP(crtc->pipe)); in vlv_psr_setup_vsc()
89 I915_WRITE(VLV_VSCSDP(crtc->pipe), val); in vlv_psr_setup_vsc()
211 I915_WRITE(VLV_PSRCTL(crtc->pipe), in vlv_psr_enable_source()
223 enum i915_pipe pipe = to_intel_crtc(crtc)->pipe; in vlv_psr_activate() local
231 I915_WRITE(VLV_PSRCTL(pipe), I915_READ(VLV_PSRCTL(pipe)) | in vlv_psr_activate()
567 VLV_PSRSTAT(crtc->pipe), in vlv_psr_disable()
573 val = I915_READ(VLV_PSRCTL(crtc->pipe)); in vlv_psr_disable()
577 I915_WRITE(VLV_PSRCTL(crtc->pipe), val); in vlv_psr_disable()
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H A Dintel_pm.c483 enum i915_pipe pipe = crtc->pipe; in vlv_get_fifo_size() local
486 switch (pipe) { in vlv_get_fifo_size()
507 MISSING_CASE(pipe); in vlv_get_fifo_size()
934 enum i915_pipe pipe; in g4x_write_wm_values() local
936 for_each_pipe(dev_priv, pipe) in g4x_write_wm_values()
937 trace_g4x_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm); in g4x_write_wm_values()
941 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | in g4x_write_wm_values()
942 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) | in g4x_write_wm_values()
943 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA)); in g4x_write_wm_values()
948 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) | in g4x_write_wm_values()
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H A Dintel_crt.c67 enum i915_pipe *pipe) in intel_crt_get_hw_state() argument
87 *pipe = PORT_TO_PIPE_CPT(tmp); in intel_crt_get_hw_state()
89 *pipe = PORT_TO_PIPE(tmp); in intel_crt_get_hw_state()
169 adpa |= PORT_TRANS_SEL_CPT(crtc->pipe); in intel_crt_set_dpms()
170 else if (crtc->pipe == 0) in intel_crt_set_dpms()
176 I915_WRITE(BCLRPAT(crtc->pipe), 0); in intel_crt_set_dpms()
267 int pipe = intel_crtc->pipe; in hsw_pre_enable_crt() local
271 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); in hsw_pre_enable_crt()
283 int pipe = intel_crtc->pipe; in hsw_enable_crt() local
289 intel_wait_for_vblank(dev_priv, pipe); in hsw_enable_crt()
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H A Dintel_dvo.c138 enum i915_pipe *pipe) in intel_dvo_get_hw_state() argument
150 *pipe = PORT_TO_PIPE(tmp); in intel_dvo_get_hw_state()
268 int pipe = crtc->pipe; in intel_dvo_pre_enable() local
279 if (pipe == 1) in intel_dvo_pre_enable()
443 enum i915_pipe pipe; in intel_dvo_init() local
476 for_each_pipe(dev_priv, pipe) { in intel_dvo_init()
477 dpll[pipe] = I915_READ(DPLL(pipe)); in intel_dvo_init()
478 I915_WRITE(DPLL(pipe), dpll[pipe] | DPLL_DVO_2X_MODE); in intel_dvo_init()
484 for_each_pipe(dev_priv, pipe) { in intel_dvo_init()
485 I915_WRITE(DPLL(pipe), dpll[pipe]); in intel_dvo_init()
/dflybsd-src/sbin/ipfw3/
H A Dipfw3dummynet.c155 struct dn_ioc_pipe pipe; in config_dummynet() local
162 memset(&pipe, 0, sizeof pipe); in config_dummynet()
168 pipe.pipe_nr = i; in config_dummynet()
170 pipe.fs.fs_nr = i; in config_dummynet()
181 pipe.fs.flags_fs |= DN_NOERROR; in config_dummynet()
191 pipe.fs.plr = (int)(d*0x7fffffff); in config_dummynet()
198 pipe.fs.qsize = getbw(av[0], &pipe.fs.flags_fs, 1024); in config_dummynet()
204 pipe.fs.rq_size = strtoul(av[0], NULL, 0); in config_dummynet()
216 pipe.fs.flow_mask.type = ETHERTYPE_IP; in config_dummynet()
217 pipe.fs.flow_mask.u.ip.dst_ip = 0; in config_dummynet()
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/dflybsd-src/sys/dev/drm/amd/display/dc/calcs/
H A Ddcn_calcs.c245 const struct pipe_ctx *pipe, in pipe_ctx_to_e2e_pipe_params() argument
249 if (pipe->top_pipe != NULL && pipe->top_pipe->plane_state == pipe->plane_state) in pipe_ctx_to_e2e_pipe_params()
251 else if (pipe->bottom_pipe != NULL && pipe->bottom_pipe->plane_state == pipe->plane_state) in pipe_ctx_to_e2e_pipe_params()
254 if (pipe->plane_res.dpp->ctx->dc->debug.optimized_watermark) { in pipe_ctx_to_e2e_pipe_params()
259 input->src.dcc = pipe->plane_state->dcc.enable ? 1 : 0; in pipe_ctx_to_e2e_pipe_params()
269 input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs-> in pipe_ctx_to_e2e_pipe_params()
270 dcc_support_pixel_format(pipe->plane_state->format, &bpe) ? 1 : 0; in pipe_ctx_to_e2e_pipe_params()
273 input->src.meta_pitch = pipe->plane_state->dcc.grph.meta_pitch; in pipe_ctx_to_e2e_pipe_params()
275 input->src.sw_mode = pipe->plane_state->tiling_info.gfx9.swizzle; in pipe_ctx_to_e2e_pipe_params()
277 input->src.viewport_width = pipe->plane_res.scl_data.viewport.width; in pipe_ctx_to_e2e_pipe_params()
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/dflybsd-src/sys/net/dummynet/
H A Dip_dummynet.c404 transmit_event(struct dn_pipe *pipe) in transmit_event() argument
408 while ((pkt = TAILQ_FIRST(&pipe->p_queue)) && in transmit_event()
410 TAILQ_REMOVE(&pipe->p_queue, pkt, dn_next); in transmit_event()
417 if ((pkt = TAILQ_FIRST(&pipe->p_queue)) != NULL) { in transmit_event()
422 heap_insert(&extract_heap, pkt->output_time, pipe); in transmit_event()
463 struct dn_pipe *p = q->fs->pipe; in ready_event()
642 dn_expire_pipe_cb(struct dn_pipe *pipe, void *dummy __unused) in dn_expire_pipe_cb() argument
644 if (pipe->idle_heap.elements > 0 && in dn_expire_pipe_cb()
645 DN_KEY_LT(pipe->idle_heap.p[0].key, pipe->V)) { in dn_expire_pipe_cb()
646 struct dn_flow_queue *q = pipe->idle_heap.p[0].object; in dn_expire_pipe_cb()
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/dflybsd-src/sys/net/dummynet3/
H A Dip_dummynet3.c423 transmit_event(struct dn_pipe *pipe) in transmit_event() argument
427 while ((pkt = TAILQ_FIRST(&pipe->p_queue)) && in transmit_event()
429 TAILQ_REMOVE(&pipe->p_queue, pkt, dn_next); in transmit_event()
436 if ((pkt = TAILQ_FIRST(&pipe->p_queue)) != NULL) { in transmit_event()
441 heap_insert(&extract_heap, pkt->output_time, pipe); in transmit_event()
482 struct dn_pipe *p = q->fs->pipe; in ready_event()
661 dn_expire_pipe_cb(struct dn_pipe *pipe, void *dummy __unused) in dn_expire_pipe_cb() argument
663 if (pipe->idle_heap.elements > 0 && in dn_expire_pipe_cb()
664 DN_KEY_LT(pipe->idle_heap.p[0].key, pipe->V)) { in dn_expire_pipe_cb()
665 struct dn_flow_queue *q = pipe->idle_heap.p[0].object; in dn_expire_pipe_cb()
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/dflybsd-src/sys/dev/drm/include/drm/
H A Ddrm_simple_kms_helper.h31 void (*enable)(struct drm_simple_display_pipe *pipe,
40 void (*disable)(struct drm_simple_display_pipe *pipe);
59 int (*check)(struct drm_simple_display_pipe *pipe,
74 void (*update)(struct drm_simple_display_pipe *pipe,
84 int (*prepare_fb)(struct drm_simple_display_pipe *pipe,
94 void (*cleanup_fb)(struct drm_simple_display_pipe *pipe,
118 int drm_simple_display_pipe_attach_bridge(struct drm_simple_display_pipe *pipe,
122 struct drm_simple_display_pipe *pipe,
/dflybsd-src/contrib/wpa_supplicant/wpa_supplicant/
H A Dctrl_iface_named_pipe.c65 HANDLE pipe; member
100 static int ctrl_broken_pipe(HANDLE pipe, int used) in ctrl_broken_pipe() argument
104 if (PeekNamedPipe(pipe, NULL, 0, NULL, NULL, NULL)) in ctrl_broken_pipe()
122 if (ctrl_broken_pipe(dst->pipe, dst->used)) { in ctrl_flush_broken_pipes()
145 dst->pipe = INVALID_HANDLE_VALUE; in ctrl_open_pipe()
167 dst->pipe = CreateNamedPipe(name, in ctrl_open_pipe()
175 if (dst->pipe == INVALID_HANDLE_VALUE) { in ctrl_open_pipe()
181 if (ConnectNamedPipe(dst->pipe, &dst->overlap)) { in ctrl_open_pipe()
184 CloseHandle(dst->pipe); in ctrl_open_pipe()
204 CloseHandle(dst->pipe); in ctrl_open_pipe()
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/dflybsd-src/sys/dev/drm/amd/display/dc/dce/
H A Ddce_hwseq.c48 struct pipe_ctx *pipe, in dce_pipe_control_lock() argument
56 if (lock && pipe->stream_res.tg->funcs->is_blanked && in dce_pipe_control_lock()
57 pipe->stream_res.tg->funcs->is_blanked(pipe->stream_res.tg)) in dce_pipe_control_lock()
60 val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], in dce_pipe_control_lock()
71 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
76 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
82 uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst]); in dce_pipe_control_lock()
83 REG_WRITE(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst], value); in dce_pipe_control_lock()
/dflybsd-src/sys/dev/drm/amd/amdgpu/
H A Damdgpu_gfx.h64 int mec, int pipe, int queue) in amdgpu_gfx_queue_to_bit() argument
70 bit += pipe * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_queue_to_bit()
77 int *mec, int *pipe, int *queue) in amdgpu_gfx_bit_to_queue() argument
80 *pipe = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_gfx_bit_to_queue()
87 int mec, int pipe, int queue) in amdgpu_gfx_is_mec_queue_enabled() argument
89 return test_bit(amdgpu_gfx_queue_to_bit(adev, mec, pipe, queue), in amdgpu_gfx_is_mec_queue_enabled()
/dflybsd-src/sys/dev/drm/amd/display/dc/dml/
H A Ddml1_display_rq_dlg_calc.c992 unsigned int htotal = e2e_pipe_param.pipe.dest.htotal; in dml1_rq_dlg_get_dlg_params()
993 unsigned int hblank_end = e2e_pipe_param.pipe.dest.hblank_end; in dml1_rq_dlg_get_dlg_params()
994 unsigned int vblank_start = e2e_pipe_param.pipe.dest.vblank_start; in dml1_rq_dlg_get_dlg_params()
995 unsigned int vblank_end = e2e_pipe_param.pipe.dest.vblank_end; in dml1_rq_dlg_get_dlg_params()
996 bool interlaced = e2e_pipe_param.pipe.dest.interlaced; in dml1_rq_dlg_get_dlg_params()
999 double pclk_freq_in_mhz = e2e_pipe_param.pipe.dest.pixel_rate_mhz; in dml1_rq_dlg_get_dlg_params()
1182 dcc_en = e2e_pipe_param.pipe.src.dcc; in dml1_rq_dlg_get_dlg_params()
1184 (enum source_format_class) e2e_pipe_param.pipe.src.source_format); in dml1_rq_dlg_get_dlg_params()
1186 …access_dir = (e2e_pipe_param.pipe.src.source_scan == dm_vert); /* vp access direction: horizontal … in dml1_rq_dlg_get_dlg_params()
1188 (enum source_format_class) e2e_pipe_param.pipe.src.source_format, in dml1_rq_dlg_get_dlg_params()
[all …]
/dflybsd-src/sys/dev/drm/amd/display/dc/core/
H A Ddc.c200 struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_adjust_vmin_vmax() local
202 if (pipe->stream == stream && pipe->stream_res.stream_enc) { in dc_stream_adjust_vmin_vmax()
203 dc->hwss.set_drr(&pipe, 1, vmin, vmax); in dc_stream_adjust_vmin_vmax()
206 resource_build_info_frame(pipe); in dc_stream_adjust_vmin_vmax()
207 dc->hwss.update_info_frame(pipe); in dc_stream_adjust_vmin_vmax()
226 struct pipe_ctx *pipe = in dc_stream_get_crtc_position() local
229 if (pipe->stream == stream && pipe->stream_res.stream_enc) { in dc_stream_get_crtc_position()
230 dc->hwss.get_position(&pipe, 1, &position); in dc_stream_get_crtc_position()
255 struct pipe_ctx *pipe; in dc_stream_configure_crc() local
260 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; in dc_stream_configure_crc()
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