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Searched refs:phy (Results 1 – 25 of 113) sorted by relevance

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/dflybsd-src/sys/netproto/802_11/wlan/
H A Dieee80211_phy.c80 [0] = { .phy = CCK, 1000, 0x00, B(2), 0 },/* 1 Mb */
81 [1] = { .phy = CCK, 2000, 0x04, B(4), 1 },/* 2 Mb */
82 [2] = { .phy = CCK, 5500, 0x04, B(11), 1 },/* 5.5 Mb */
83 [3] = { .phy = CCK, 11000, 0x04, B(22), 1 },/* 11 Mb */
84 [4] = { .phy = PBCC, 22000, 0x04, 44, 3 } /* 22 Mb */
93 [0] = { .phy = CCK, 1000, 0x00, B(2), 0 },
94 [1] = { .phy = CCK, 2000, 0x04, B(4), 1 },
95 [2] = { .phy = CCK, 5500, 0x04, B(11), 2 },
96 [3] = { .phy = CCK, 11000, 0x04, B(22), 3 },
97 [4] = { .phy = OFDM, 6000, 0x00, 12, 4 },
[all …]
/dflybsd-src/sys/dev/netif/ig_hal/
H A De1000_phy.c72 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_ops_generic() local
76 phy->ops.init_params = e1000_null_ops_generic; in e1000_init_phy_ops_generic()
77 phy->ops.acquire = e1000_null_ops_generic; in e1000_init_phy_ops_generic()
78 phy->ops.check_polarity = e1000_null_ops_generic; in e1000_init_phy_ops_generic()
79 phy->ops.check_reset_block = e1000_null_ops_generic; in e1000_init_phy_ops_generic()
80 phy->ops.commit = e1000_null_ops_generic; in e1000_init_phy_ops_generic()
81 phy->ops.force_speed_duplex = e1000_null_ops_generic; in e1000_init_phy_ops_generic()
82 phy->ops.get_cfg_done = e1000_null_ops_generic; in e1000_init_phy_ops_generic()
83 phy->ops.get_cable_length = e1000_null_ops_generic; in e1000_init_phy_ops_generic()
84 phy->ops.get_info = e1000_null_ops_generic; in e1000_init_phy_ops_generic()
[all …]
H A De1000_82541.c86 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_82541() local
91 phy->addr = 1; in e1000_init_phy_params_82541()
92 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_init_phy_params_82541()
93 phy->reset_delay_us = 10000; in e1000_init_phy_params_82541()
94 phy->type = e1000_phy_igp; in e1000_init_phy_params_82541()
97 phy->ops.check_polarity = e1000_check_polarity_igp; in e1000_init_phy_params_82541()
98 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; in e1000_init_phy_params_82541()
99 phy->ops.get_cable_length = e1000_get_cable_length_igp_82541; in e1000_init_phy_params_82541()
100 phy->ops.get_cfg_done = e1000_get_cfg_done_generic; in e1000_init_phy_params_82541()
101 phy->ops.get_info = e1000_get_phy_info_igp; in e1000_init_phy_params_82541()
[all …]
H A De1000_82575.c165 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_82575() local
171 phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic; in e1000_init_phy_params_82575()
172 phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic; in e1000_init_phy_params_82575()
174 if (hw->phy.media_type != e1000_media_type_copper) { in e1000_init_phy_params_82575()
175 phy->type = e1000_phy_none; in e1000_init_phy_params_82575()
179 phy->ops.power_up = e1000_power_up_phy_copper; in e1000_init_phy_params_82575()
180 phy->ops.power_down = e1000_power_down_phy_copper_82575; in e1000_init_phy_params_82575()
182 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_init_phy_params_82575()
183 phy->reset_delay_us = 100; in e1000_init_phy_params_82575()
185 phy->ops.acquire = e1000_acquire_phy_82575; in e1000_init_phy_params_82575()
[all …]
H A De1000_ich8lan.c209 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_reg); in e1000_phy_is_accessible_pchlan()
214 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_reg); in e1000_phy_is_accessible_pchlan()
223 if (hw->phy.id) { in e1000_phy_is_accessible_pchlan()
224 if (hw->phy.id == phy_id) in e1000_phy_is_accessible_pchlan()
227 hw->phy.id = phy_id; in e1000_phy_is_accessible_pchlan()
228 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK); in e1000_phy_is_accessible_pchlan()
236 hw->phy.ops.release(hw); in e1000_phy_is_accessible_pchlan()
240 hw->phy.ops.acquire(hw); in e1000_phy_is_accessible_pchlan()
251 hw->phy.ops.read_reg_locked(hw, CV_SMB_CTRL, &phy_reg); in e1000_phy_is_accessible_pchlan()
253 hw->phy.ops.write_reg_locked(hw, CV_SMB_CTRL, phy_reg); in e1000_phy_is_accessible_pchlan()
[all …]
H A De1000_82571.c96 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_82571() local
101 if (hw->phy.media_type != e1000_media_type_copper) { in e1000_init_phy_params_82571()
102 phy->type = e1000_phy_none; in e1000_init_phy_params_82571()
106 phy->addr = 1; in e1000_init_phy_params_82571()
107 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_init_phy_params_82571()
108 phy->reset_delay_us = 100; in e1000_init_phy_params_82571()
110 phy->ops.check_reset_block = e1000_check_reset_block_generic; in e1000_init_phy_params_82571()
111 phy->ops.reset = e1000_phy_hw_reset_generic; in e1000_init_phy_params_82571()
112 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82571; in e1000_init_phy_params_82571()
113 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; in e1000_init_phy_params_82571()
[all …]
H A De1000_80003es2lan.c91 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_80003es2lan() local
96 if (hw->phy.media_type != e1000_media_type_copper) { in e1000_init_phy_params_80003es2lan()
97 phy->type = e1000_phy_none; in e1000_init_phy_params_80003es2lan()
100 phy->ops.power_up = e1000_power_up_phy_copper; in e1000_init_phy_params_80003es2lan()
101 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan; in e1000_init_phy_params_80003es2lan()
104 phy->addr = 1; in e1000_init_phy_params_80003es2lan()
105 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_init_phy_params_80003es2lan()
106 phy->reset_delay_us = 100; in e1000_init_phy_params_80003es2lan()
107 phy->type = e1000_phy_gg82563; in e1000_init_phy_params_80003es2lan()
109 phy->ops.acquire = e1000_acquire_phy_80003es2lan; in e1000_init_phy_params_80003es2lan()
[all …]
H A De1000_82540.c68 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_82540() local
71 phy->addr = 1; in e1000_init_phy_params_82540()
72 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_init_phy_params_82540()
73 phy->reset_delay_us = 10000; in e1000_init_phy_params_82540()
74 phy->type = e1000_phy_m88; in e1000_init_phy_params_82540()
77 phy->ops.check_polarity = e1000_check_polarity_m88; in e1000_init_phy_params_82540()
78 phy->ops.commit = e1000_phy_sw_reset_generic; in e1000_init_phy_params_82540()
79 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; in e1000_init_phy_params_82540()
80 phy->ops.get_cable_length = e1000_get_cable_length_m88; in e1000_init_phy_params_82540()
81 phy->ops.get_cfg_done = e1000_get_cfg_done_generic; in e1000_init_phy_params_82540()
[all …]
H A De1000_82543.c84 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_82543() local
89 if (hw->phy.media_type != e1000_media_type_copper) { in e1000_init_phy_params_82543()
90 phy->type = e1000_phy_none; in e1000_init_phy_params_82543()
93 phy->ops.power_up = e1000_power_up_phy_copper; in e1000_init_phy_params_82543()
94 phy->ops.power_down = e1000_power_down_phy_copper; in e1000_init_phy_params_82543()
97 phy->addr = 1; in e1000_init_phy_params_82543()
98 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_init_phy_params_82543()
99 phy->reset_delay_us = 10000; in e1000_init_phy_params_82543()
100 phy->type = e1000_phy_m88; in e1000_init_phy_params_82543()
103 phy->ops.check_polarity = e1000_check_polarity_m88; in e1000_init_phy_params_82543()
[all …]
H A De1000_api.c100 if (hw->phy.ops.init_params) { in e1000_init_phy_params()
101 ret_val = hw->phy.ops.init_params(hw); in e1000_init_phy_params()
1000 if (hw->phy.ops.check_reset_block) in e1000_check_reset_block()
1001 return hw->phy.ops.check_reset_block(hw); in e1000_check_reset_block()
1017 if (hw->phy.ops.read_reg) in e1000_read_phy_reg()
1018 return hw->phy.ops.read_reg(hw, offset, data); in e1000_read_phy_reg()
1034 if (hw->phy.ops.write_reg) in e1000_write_phy_reg()
1035 return hw->phy.ops.write_reg(hw, offset, data); in e1000_write_phy_reg()
1049 if (hw->phy.ops.release) in e1000_release_phy()
1050 hw->phy.ops.release(hw); in e1000_release_phy()
[all …]
/dflybsd-src/sys/dev/netif/ix/
H A Dixgbe_phy.c116 u32 swfw_mask = hw->phy.phy_semaphore_mask; in ixgbe_read_i2c_combined_generic_int()
194 u32 swfw_mask = hw->phy.phy_semaphore_mask; in ixgbe_write_i2c_combined_generic_int()
254 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_init_phy_ops_generic() local
259 phy->ops.identify = ixgbe_identify_phy_generic; in ixgbe_init_phy_ops_generic()
260 phy->ops.reset = ixgbe_reset_phy_generic; in ixgbe_init_phy_ops_generic()
261 phy->ops.read_reg = ixgbe_read_phy_reg_generic; in ixgbe_init_phy_ops_generic()
262 phy->ops.write_reg = ixgbe_write_phy_reg_generic; in ixgbe_init_phy_ops_generic()
263 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi; in ixgbe_init_phy_ops_generic()
264 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi; in ixgbe_init_phy_ops_generic()
265 phy->ops.setup_link = ixgbe_setup_phy_link_generic; in ixgbe_init_phy_ops_generic()
[all …]
H A Dixgbe_x550.c253 u32 swfw_mask = hw->phy.phy_semaphore_mask; in ixgbe_check_cs4227()
365 hw->phy.type = ixgbe_phy_x550em_kx4; in ixgbe_identify_phy_x550em()
368 hw->phy.type = ixgbe_phy_x550em_xfi; in ixgbe_identify_phy_x550em()
373 hw->phy.type = ixgbe_phy_x550em_kr; in ixgbe_identify_phy_x550em()
379 hw->phy.type = ixgbe_phy_ext_1g_t; in ixgbe_identify_phy_x550em()
383 hw->phy.type = ixgbe_phy_fw; in ixgbe_identify_phy_x550em()
385 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM; in ixgbe_identify_phy_x550em()
387 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM; in ixgbe_identify_phy_x550em()
471 hw->phy.speeds_supported = 0; in ixgbe_get_phy_id_fw()
475 hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed; in ixgbe_get_phy_id_fw()
[all …]
H A Dixgbe_82598.c122 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_init_ops_82598() local
131 phy->ops.init = ixgbe_init_phy_ops_82598; in ixgbe_init_ops_82598()
164 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_82598; in ixgbe_init_ops_82598()
165 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_82598; in ixgbe_init_ops_82598()
194 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_init_phy_ops_82598() local
201 phy->ops.identify(hw); in ixgbe_init_phy_ops_82598()
210 switch (hw->phy.type) { in ixgbe_init_phy_ops_82598()
212 phy->ops.setup_link = ixgbe_setup_phy_link_tnx; in ixgbe_init_phy_ops_82598()
213 phy->ops.check_link = ixgbe_check_phy_link_tnx; in ixgbe_init_phy_ops_82598()
214 phy->ops.get_firmware_version = in ixgbe_init_phy_ops_82598()
[all …]
H A Dixgbe_82599.c85 if (hw->phy.multispeed_fiber) { in ixgbe_init_mac_link_ops_82599()
96 (hw->phy.smart_speed == ixgbe_smart_speed_auto || in ixgbe_init_mac_link_ops_82599()
97 hw->phy.smart_speed == ixgbe_smart_speed_on) && in ixgbe_init_mac_link_ops_82599()
118 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_init_phy_ops_82599() local
126 hw->phy.qsfp_shared_i2c_bus = TRUE; in ixgbe_init_phy_ops_82599()
138 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_82599; in ixgbe_init_phy_ops_82599()
139 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_82599; in ixgbe_init_phy_ops_82599()
142 ret_val = phy->ops.identify(hw); in ixgbe_init_phy_ops_82599()
148 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) in ixgbe_init_phy_ops_82599()
149 hw->phy.ops.reset = NULL; in ixgbe_init_phy_ops_82599()
[all …]
H A Dixgbe_api.c476 if (hw->phy.type == ixgbe_phy_unknown) { in ixgbe_identify_phy()
477 status = ixgbe_call_func(hw, hw->phy.ops.identify, (hw), in ixgbe_identify_phy()
492 if (hw->phy.type == ixgbe_phy_unknown) { in ixgbe_reset_phy()
498 status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw), in ixgbe_reset_phy()
513 status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version, in ixgbe_get_phy_firmware_version()
531 if (hw->phy.id == 0) in ixgbe_read_phy_reg()
534 return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr, in ixgbe_read_phy_reg()
550 if (hw->phy.id == 0) in ixgbe_write_phy_reg()
553 return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr, in ixgbe_write_phy_reg()
565 return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw), in ixgbe_setup_phy_link()
[all …]
/dflybsd-src/tools/tools/net80211/wlantxtime/
H A Dwlantxtime.c53 uint8_t phy; /* CCK/OFDM/TURBO */ member
104 [0] = { .phy = CCK, 1000, 0x00, B(2), 0 },/* 1 Mb */
105 [1] = { .phy = CCK, 2000, 0x04, B(4), 1 },/* 2 Mb */
106 [2] = { .phy = CCK, 5500, 0x04, B(11), 1 },/* 5.5 Mb */
107 [3] = { .phy = CCK, 11000, 0x04, B(22), 1 },/* 11 Mb */
108 [4] = { .phy = PBCC, 22000, 0x04, 44, 3 } /* 22 Mb */
117 [0] = { .phy = CCK, 1000, 0x00, B(2), 0 },
118 [1] = { .phy = CCK, 2000, 0x04, B(4), 1 },
119 [2] = { .phy = CCK, 5500, 0x04, B(11), 2 },
120 [3] = { .phy = CCK, 11000, 0x04, B(22), 3 },
[all …]
/dflybsd-src/sys/dev/netif/bwn/bwn/
H A Dif_bwn_phy_g.c179 struct bwn_phy *phy = &mac->mac_phy; in bwn_phy_g_attach() local
180 struct bwn_phy_g *pg = &phy->phy_g; in bwn_phy_g_attach()
191 if ((siba_get_chipid(sc->sc_dev) == 0x4301) && (phy->rf_ver != 0x2050)) in bwn_phy_g_attach()
253 struct bwn_phy *phy = &mac->mac_phy; in bwn_phy_g_init_pre() local
254 struct bwn_phy_g *pg = &phy->phy_g; in bwn_phy_g_init_pre()
286 struct bwn_phy *phy = &mac->mac_phy; in bwn_phy_g_prepare_hw() local
287 struct bwn_phy_g *pg = &phy->phy_g; in bwn_phy_g_prepare_hw()
307 KASSERT(phy->type == BWN_PHYTYPE_G, ("%s fail", __func__)); in bwn_phy_g_prepare_hw()
309 if (phy->rf_ver == 0x2050 && phy->rf_rev < 6) in bwn_phy_g_prepare_hw()
328 if (phy->type == BWN_PHYTYPE_A) { in bwn_phy_g_prepare_hw()
[all …]
/dflybsd-src/sys/dev/drm/i915/
H A Dintel_dpio_phy.c224 bxt_get_phy_info(struct drm_i915_private *dev_priv, enum dpio_phy phy) in bxt_get_phy_info() argument
230 return &phy_list[phy]; in bxt_get_phy_info()
234 enum dpio_phy *phy, enum dpio_channel *ch) in bxt_port_to_phy_channel() argument
245 *phy = i; in bxt_port_to_phy_channel()
252 *phy = i; in bxt_port_to_phy_channel()
259 *phy = DPIO_PHY0; in bxt_port_to_phy_channel()
268 enum dpio_phy phy; in bxt_ddi_phy_set_signal_level() local
271 bxt_port_to_phy_channel(dev_priv, port, &phy, &ch); in bxt_ddi_phy_set_signal_level()
277 val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch)); in bxt_ddi_phy_set_signal_level()
279 I915_WRITE(BXT_PORT_PCS_DW10_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_level()
[all …]
H A Dintel_dpll_mgr.c1434 enum dpio_phy phy; in bxt_ddi_pll_enable() local
1437 bxt_port_to_phy_channel(dev_priv, port, &phy, &ch); in bxt_ddi_pll_enable()
1455 temp = I915_READ(BXT_PORT_PLL_EBB_4(phy, ch)); in bxt_ddi_pll_enable()
1457 I915_WRITE(BXT_PORT_PLL_EBB_4(phy, ch), temp); in bxt_ddi_pll_enable()
1460 temp = I915_READ(BXT_PORT_PLL_EBB_0(phy, ch)); in bxt_ddi_pll_enable()
1463 I915_WRITE(BXT_PORT_PLL_EBB_0(phy, ch), temp); in bxt_ddi_pll_enable()
1466 temp = I915_READ(BXT_PORT_PLL(phy, ch, 0)); in bxt_ddi_pll_enable()
1469 I915_WRITE(BXT_PORT_PLL(phy, ch, 0), temp); in bxt_ddi_pll_enable()
1472 temp = I915_READ(BXT_PORT_PLL(phy, ch, 1)); in bxt_ddi_pll_enable()
1475 I915_WRITE(BXT_PORT_PLL(phy, ch, 1), temp); in bxt_ddi_pll_enable()
[all …]
H A Dintel_runtime_pm.c661 bxt_ddi_phy_init(dev_priv, power_well->bxt.phy); in bxt_dpio_cmn_power_well_enable()
667 bxt_ddi_phy_uninit(dev_priv, power_well->bxt.phy); in bxt_dpio_cmn_power_well_disable()
673 return bxt_ddi_phy_is_enabled(dev_priv, power_well->bxt.phy); in bxt_dpio_cmn_power_well_enabled()
682 bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy); in bxt_verify_ddi_phy_power_wells()
686 bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy); in bxt_verify_ddi_phy_power_wells()
691 bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy); in bxt_verify_ddi_phy_power_wells()
1155 enum dpio_phy phy; in chv_dpio_cmn_power_well_enable() local
1164 phy = DPIO_PHY0; in chv_dpio_cmn_power_well_enable()
1167 phy = DPIO_PHY1; in chv_dpio_cmn_power_well_enable()
1177 PHY_POWERGOOD(phy), in chv_dpio_cmn_power_well_enable()
[all …]
/dflybsd-src/sys/dev/netif/mii_layer/
H A Dukphy_subr.c66 ukphy_status(struct mii_softc *phy) in ukphy_status() argument
68 struct mii_data *mii = phy->mii_pdata; in ukphy_status()
74 bmsr = PHY_READ(phy, MII_BMSR) | PHY_READ(phy, MII_BMSR); in ukphy_status()
78 bmcr = PHY_READ(phy, MII_BMCR); in ukphy_status()
100 anlpar = PHY_READ(phy, MII_ANAR) & PHY_READ(phy, MII_ANLPAR); in ukphy_status()
101 if ((phy->mii_flags & MIIF_HAVE_GTCR) != 0 && in ukphy_status()
102 (phy->mii_extcapabilities & in ukphy_status()
104 gtcr = PHY_READ(phy, MII_100T2CR); in ukphy_status()
105 gtsr = PHY_READ(phy, MII_100T2SR); in ukphy_status()
133 mii->mii_media_active |= mii_phy_flowstatus(phy); in ukphy_status()
/dflybsd-src/sys/bus/u4b/net/
H A Druephy.c192 ruephy_status(struct mii_softc *phy) in ruephy_status() argument
194 struct mii_data *mii = phy->mii_pdata; in ruephy_status()
201 msr = PHY_READ(phy, RUEPHY_MII_MSR) | PHY_READ(phy, RUEPHY_MII_MSR); in ruephy_status()
205 bmcr = PHY_READ(phy, MII_BMCR); in ruephy_status()
212 bmsr = PHY_READ(phy, MII_BMSR) | PHY_READ(phy, MII_BMSR); in ruephy_status()
227 IFM_FDX | mii_phy_flowstatus(phy); in ruephy_status()
/dflybsd-src/bin/pwd/
H A Dpwd.c96 struct stat logic, phy; in getcwd_logical() local
104 if (stat(pwd, &logic) == -1 || stat(".", &phy) == -1) in getcwd_logical()
106 if (logic.st_dev == phy.st_dev && logic.st_ino == phy.st_ino) in getcwd_logical()
/dflybsd-src/contrib/wpa_supplicant/src/drivers/
H A Drfkill.c108 char *phy = NULL, *rfk_phy; in rfkill_init() local
119 phy = realpath(buf, NULL); in rfkill_init()
120 if (!phy) { in rfkill_init()
163 found = os_strcmp(phy, rfk_phy) == 0; in rfkill_init()
188 free(phy); in rfkill_init()
198 free(phy); in rfkill_init()
/dflybsd-src/sys/dev/netif/tx/
H A Dif_txvar.h119 #define PHY_READ_2(sc, phy, reg) \ argument
120 epic_read_phy_reg((sc), (phy), (reg))
121 #define PHY_WRITE_2(sc, phy, reg, val) \ argument
122 epic_write_phy_reg((sc), (phy), (reg), (val))

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