| /dflybsd-src/sys/dev/drm/amd/display/dc/dce110/ |
| H A D | dce110_opp_regamma_v.c | 68 dm_write_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL, value); in power_on_lut() 97 dm_write_reg(xfm_dce->base.ctx, in set_bypass_input_gamma() 111 dm_write_reg(xfm_dce->base.ctx, mmGAMMA_CORR_CONTROL, 0); in configure_regamma_mode() 149 dm_write_reg(xfm_dce->base.ctx, mmGAMMA_CORR_CNTLA_START_CNTL, in regamma_config_regions_and_segments() 160 dm_write_reg(xfm_dce->base.ctx, in regamma_config_regions_and_segments() 171 dm_write_reg(xfm_dce->base.ctx, in regamma_config_regions_and_segments() 188 dm_write_reg(xfm_dce->base.ctx, in regamma_config_regions_and_segments() 220 dm_write_reg( in regamma_config_regions_and_segments() 253 dm_write_reg(xfm_dce->base.ctx, in regamma_config_regions_and_segments() 285 dm_write_reg(xfm_dce->base.ctx, in regamma_config_regions_and_segments() [all …]
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| H A D | dce110_mem_input_v.c | 54 dm_write_reg( in set_flip_control() 75 dm_write_reg( in program_pri_addr_c() 89 dm_write_reg( in program_pri_addr_c() 111 dm_write_reg( in program_pri_addr_l() 125 dm_write_reg( in program_pri_addr_l() 161 dm_write_reg(mem_input110->base.ctx, in enable() 203 dm_write_reg( in program_tiling() 225 dm_write_reg( in program_tiling() 256 dm_write_reg( in program_size_and_rotation() 264 dm_write_reg( in program_size_and_rotation() [all …]
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| H A D | dce110_opp_csc_v.c | 142 dm_write_reg(ctx, addr, value); in program_color_matrix_v() 160 dm_write_reg(ctx, addr, value); in program_color_matrix_v() 178 dm_write_reg(ctx, addr, value); in program_color_matrix_v() 196 dm_write_reg(ctx, addr, value); in program_color_matrix_v() 214 dm_write_reg(ctx, addr, value); in program_color_matrix_v() 232 dm_write_reg(ctx, addr, value); in program_color_matrix_v() 256 dm_write_reg(ctx, addr, value); in program_color_matrix_v() 274 dm_write_reg(ctx, addr, value); in program_color_matrix_v() 292 dm_write_reg(ctx, addr, value); in program_color_matrix_v() 310 dm_write_reg(ctx, addr, value); in program_color_matrix_v() [all …]
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| H A D | dce110_timing_generator.c | 116 dm_write_reg(tg->ctx, address, regval); in dce110_timing_generator_set_early_control() 140 dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_MODE), value); in dce110_timing_generator_enable_crtc() 144 dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_LOCK), value); in dce110_timing_generator_enable_crtc() 175 dm_write_reg(tg->ctx, addr, value); in dce110_timing_generator_program_blank_color() 222 dm_write_reg(tg->ctx, addr, value); 225 dm_write_reg(tg->ctx, addr, value); 272 dm_write_reg(tg->ctx, in program_horz_count_by_2() 461 dm_write_reg(tg->ctx, addr, v_total_min); in dce110_timing_generator_set_drr() 464 dm_write_reg(tg->ctx, addr, v_total_max); in dce110_timing_generator_set_drr() 467 dm_write_reg(tg->ctx, addr, v_total_cntl); in dce110_timing_generator_set_drr() [all …]
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| H A D | dce110_timing_generator_v.c | 65 dm_write_reg(tg->ctx, in dce110_timing_generator_v_enable_crtc() 70 dm_write_reg(tg->ctx, mmCRTCV_MASTER_UPDATE_MODE, value); in dce110_timing_generator_v_enable_crtc() 75 dm_write_reg(tg->ctx, in dce110_timing_generator_v_enable_crtc() 91 dm_write_reg(tg->ctx, in dce110_timing_generator_v_disable_crtc() 117 dm_write_reg(tg->ctx, addr, value); in dce110_timing_generator_v_blank_crtc() 137 dm_write_reg(tg->ctx, addr, value); in dce110_timing_generator_v_unblank_crtc() 266 dm_write_reg(ctx, addr, value); in dce110_timing_generator_v_program_blanking() 275 dm_write_reg(ctx, addr, value); in dce110_timing_generator_v_program_blanking() 298 dm_write_reg(ctx, addr, value); in dce110_timing_generator_v_program_blanking() 320 dm_write_reg(ctx, addr, value); in dce110_timing_generator_v_program_blanking() [all …]
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| H A D | dce110_compressor.c | 121 dm_write_reg(ctx, mmLB_SYNC_RESET_SEL, value); in reset_lb_on_vblank() 138 dm_write_reg(ctx, mmLB_SYNC_RESET_SEL, value); in reset_lb_on_vblank() 191 dm_write_reg(compressor->ctx, addr, value); in dce110_compressor_power_up_fbc() 198 dm_write_reg(compressor->ctx, addr, value); in dce110_compressor_power_up_fbc() 203 dm_write_reg(compressor->ctx, addr, value); in dce110_compressor_power_up_fbc() 209 dm_write_reg(compressor->ctx, addr, value); in dce110_compressor_power_up_fbc() 213 dm_write_reg(compressor->ctx, mmFBC_IND_LUT0, value); in dce110_compressor_power_up_fbc() 216 dm_write_reg(compressor->ctx, mmFBC_IND_LUT1, value); in dce110_compressor_power_up_fbc() 239 dm_write_reg(compressor->ctx, addr, value); in dce110_compressor_enable_fbc() 248 dm_write_reg(compressor->ctx, addr, value); in dce110_compressor_enable_fbc() [all …]
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| H A D | dce110_transform_v.c | 99 dm_write_reg(ctx, addr, value); in program_viewport() 113 dm_write_reg(ctx, addr, value); in program_viewport() 129 dm_write_reg(ctx, addr, value); in program_viewport() 143 dm_write_reg(ctx, addr, value); in program_viewport() 173 dm_write_reg(ctx, mmSCLV_TAP_CONTROL, value); in setup_scaling_configuration() 204 dm_write_reg(ctx, mmSCLV_MODE, value); in setup_scaling_configuration() 213 dm_write_reg(ctx, mmSCLV_CONTROL, value); in setup_scaling_configuration() 264 dm_write_reg(xfm_dce->base.ctx, in program_overscan() 268 dm_write_reg(xfm_dce->base.ctx, in program_overscan() 280 dm_write_reg(xfm_dce->base.ctx, mmSCLV_UPDATE, value); in set_coeff_update_complete() [all …]
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| H A D | dce110_hw_sequencer.c | 141 dm_write_reg(ctx, addr, value); in dce110_init_pte() 176 dm_write_reg(ctx, addr, value); in dce110_init_pte() 225 dm_write_reg(ctx, in dce110_enable_display_power_gating()
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| /dflybsd-src/sys/dev/drm/amd/display/dc/dce112/ |
| H A D | dce112_compressor.c | 334 dm_write_reg(compressor->ctx, addr, value); in dce112_compressor_power_up_fbc() 341 dm_write_reg(compressor->ctx, addr, value); in dce112_compressor_power_up_fbc() 346 dm_write_reg(compressor->ctx, addr, value); in dce112_compressor_power_up_fbc() 352 dm_write_reg(compressor->ctx, addr, value); in dce112_compressor_power_up_fbc() 356 dm_write_reg(compressor->ctx, mmFBC_IND_LUT0, value); in dce112_compressor_power_up_fbc() 359 dm_write_reg(compressor->ctx, mmFBC_IND_LUT1, value); in dce112_compressor_power_up_fbc() 397 dm_write_reg(compressor->ctx, addr, value); in dce112_compressor_enable_fbc() 406 dm_write_reg(compressor->ctx, addr, value); in dce112_compressor_enable_fbc() 408 dm_write_reg(compressor->ctx, addr, value); in dce112_compressor_enable_fbc() 424 dm_write_reg(compressor->ctx, mmFBC_CNTL, reg_data); in dce112_compressor_disable_fbc() [all …]
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| H A D | dce112_hw_sequencer.c | 109 dm_write_reg(ctx, addr, value); in dce112_init_pte() 141 dm_write_reg(ctx, in dce112_enable_display_power_gating()
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| /dflybsd-src/sys/dev/drm/amd/display/dc/i2caux/dce80/ |
| H A D | i2c_hw_engine_dce80.c | 112 dm_write_reg(ctx, addr, value); in disable_i2c_hw_engine() 140 dm_write_reg(engine->ctx, mmDC_I2C_ARBITRATION, value); in release_engine() 172 dm_write_reg(engine->ctx, mmDC_I2C_CONTROL, value); in release_engine() 246 dm_write_reg(i2c_engine->base.ctx, addr, value); in setup_engine() 267 dm_write_reg(i2c_engine->base.ctx, addr, value); in setup_engine() 290 dm_write_reg(i2c_engine->base.ctx, in setup_engine() 344 dm_write_reg(i2c_engine->base.ctx, addr, value); in set_speed() 364 dm_write_reg(engine->ctx, mmDC_I2C_CONTROL, value); in reset_hw_engine() 467 dm_write_reg(ctx, addr, value); in process_transaction() 507 dm_write_reg(ctx, mmDC_I2C_DATA, value); in process_transaction() [all …]
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| /dflybsd-src/sys/dev/drm/amd/display/dc/dce/ |
| H A D | dce_dmcu.c | 239 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), in dce_dmcu_setup_psr() 251 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2), in dce_dmcu_setup_psr() 256 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3), in dce_dmcu_setup_psr() 304 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); in dce_psr_wait_loop() 658 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), in dcn10_dmcu_setup_psr() 670 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2), in dcn10_dmcu_setup_psr() 675 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3), in dcn10_dmcu_setup_psr() 709 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); in dcn10_psr_wait_loop()
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| H A D | dce_link_encoder.c | 498 dm_write_reg(ctx, addr, value); in aux_initialize() 506 dm_write_reg(ctx, addr, value); in aux_initialize()
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| /dflybsd-src/sys/dev/drm/amd/display/dc/irq/ |
| H A D | irq_service.c | 98 dm_write_reg(irq_service->ctx, addr, value); in dal_irq_service_set_generic() 135 dm_write_reg(irq_service->ctx, addr, value); in dal_irq_service_ack_generic()
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| /dflybsd-src/sys/dev/drm/amd/display/dc/dce120/ |
| H A D | dce120_hw_sequencer.c | 147 dm_write_reg(ctx, addr, value); 182 dm_write_reg(ctx, in dce120_enable_display_power_gating()
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| /dflybsd-src/sys/dev/drm/amd/display/dc/dce80/ |
| H A D | dce80_timing_generator.c | 105 dm_write_reg(tg->ctx, addr, value); in program_pix_dur() 177 dm_write_reg(tg->ctx, addr, value); in dce80_timing_generator_enable_advanced_request()
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| /dflybsd-src/sys/dev/drm/amd/display/dc/ |
| H A D | dc_helper.c | 54 dm_write_reg(ctx, addr, reg_val); in generic_reg_update_ex() 310 dm_write_reg(ctx, addr_index, index); in generic_write_indirect_reg() 311 dm_write_reg(ctx, addr_data, data); in generic_write_indirect_reg() 323 dm_write_reg(ctx, addr_index, index); in generic_read_indirect_reg()
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| H A D | dm_services.h | 77 #define dm_write_reg(ctx, address, value) \ macro
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| /dflybsd-src/sys/dev/drm/amd/display/dc/dce100/ |
| H A D | dce100_hw_sequencer.c | 97 dm_write_reg(ctx, in dce100_enable_display_power_gating()
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| /dflybsd-src/sys/dev/drm/amd/display/dc/irq/dce80/ |
| H A D | irq_service_dce80.c | 62 dm_write_reg(irq_service->ctx, info->enable_reg, value); in hpd_ack()
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| /dflybsd-src/sys/dev/drm/amd/display/dc/irq/dce120/ |
| H A D | irq_service_dce120.c | 62 dm_write_reg(irq_service->ctx, info->enable_reg, value); in hpd_ack()
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| /dflybsd-src/sys/dev/drm/amd/display/dc/irq/dcn10/ |
| H A D | irq_service_dcn10.c | 132 dm_write_reg(irq_service->ctx, info->enable_reg, value); in hpd_ack()
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| /dflybsd-src/sys/dev/drm/amd/display/dc/irq/dce110/ |
| H A D | irq_service_dce110.c | 59 dm_write_reg(irq_service->ctx, info->enable_reg, value); in hpd_ack()
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| /dflybsd-src/sys/dev/drm/amd/display/dc/inc/ |
| H A D | reg_helper.h | 43 dm_write_reg(CTX, REG(reg_name), value)
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