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/dflybsd-src/sys/dev/drm/amd/amdgpu/
H A Damdgpu_afmt.c51 static void amdgpu_afmt_calc_cts(uint32_t clock, int *CTS, int *N, int freq) in amdgpu_afmt_calc_cts() argument
58 cts = clock * 1000; in amdgpu_afmt_calc_cts()
88 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock) in amdgpu_afmt_acr() argument
95 if (amdgpu_afmt_predefined_acr[i].clock == clock) in amdgpu_afmt_acr()
100 amdgpu_afmt_calc_cts(clock, &res.cts_32khz, &res.n_32khz, 32000); in amdgpu_afmt_acr()
101 amdgpu_afmt_calc_cts(clock, &res.cts_44_1khz, &res.n_44_1khz, 44100); in amdgpu_afmt_acr()
102 amdgpu_afmt_calc_cts(clock, &res.cts_48khz, &res.n_48khz, 48000); in amdgpu_afmt_acr()
H A Datombios_crtc.c314 u32 adjusted_clock = mode->clock; in amdgpu_atombios_crtc_adjust_pll()
316 u32 dp_clock = mode->clock; in amdgpu_atombios_crtc_adjust_pll()
317 u32 clock = mode->clock; in amdgpu_atombios_crtc_adjust_pll() local
319 bool is_duallink = amdgpu_dig_monitor_is_duallink(encoder, mode->clock); in amdgpu_atombios_crtc_adjust_pll()
350 adjusted_clock = mode->clock * 2; in amdgpu_atombios_crtc_adjust_pll()
364 clock = (clock * 5) / 4; in amdgpu_atombios_crtc_adjust_pll()
367 clock = (clock * 3) / 2; in amdgpu_atombios_crtc_adjust_pll()
370 clock = clock * 2; in amdgpu_atombios_crtc_adjust_pll()
391 args.v1.usPixelClock = cpu_to_le16(clock / 10); in amdgpu_atombios_crtc_adjust_pll()
403 args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10); in amdgpu_atombios_crtc_adjust_pll()
[all …]
H A Damdgpu_atombios.c568 struct amdgpu_pll *ppll = &adev->clock.ppll[0]; in amdgpu_atombios_get_clock_info()
569 struct amdgpu_pll *spll = &adev->clock.spll; in amdgpu_atombios_get_clock_info()
570 struct amdgpu_pll *mpll = &adev->clock.mpll; in amdgpu_atombios_get_clock_info()
612 adev->clock.ppll[i] = *ppll; in amdgpu_atombios_get_clock_info()
660 adev->clock.default_sclk = in amdgpu_atombios_get_clock_info()
662 adev->clock.default_mclk = in amdgpu_atombios_get_clock_info()
674 adev->clock.default_dispclk = in amdgpu_atombios_get_clock_info()
677 if (adev->clock.default_dispclk < 53900) { in amdgpu_atombios_get_clock_info()
679 adev->clock.default_dispclk / 100); in amdgpu_atombios_get_clock_info()
680 adev->clock.default_dispclk = 60000; in amdgpu_atombios_get_clock_info()
[all …]
/dflybsd-src/sys/dev/drm/radeon/
H A Dradeon_clocks.c38 struct radeon_pll *spll = &rdev->clock.spll; in radeon_legacy_get_engine_clock()
68 struct radeon_pll *mpll = &rdev->clock.mpll; in radeon_legacy_get_memory_clock()
105 struct radeon_pll *p1pll = &rdev->clock.p1pll; in radeon_read_clocks_OF()
106 struct radeon_pll *p2pll = &rdev->clock.p2pll; in radeon_read_clocks_OF()
107 struct radeon_pll *spll = &rdev->clock.spll; in radeon_read_clocks_OF()
108 struct radeon_pll *mpll = &rdev->clock.mpll; in radeon_read_clocks_OF()
144 rdev->clock.max_pixel_clock = 35000; in radeon_read_clocks_OF()
153 rdev->clock.default_sclk = (*val) / 10; in radeon_read_clocks_OF()
155 rdev->clock.default_sclk = in radeon_read_clocks_OF()
160 rdev->clock.default_mclk = (*val) / 10; in radeon_read_clocks_OF()
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H A Dradeon_audio.c73 struct radeon_crtc *crtc, unsigned int clock);
75 struct radeon_crtc *crtc, unsigned int clock);
77 struct radeon_crtc *crtc, unsigned int clock);
79 struct radeon_crtc *crtc, unsigned int clock);
81 struct radeon_crtc *crtc, unsigned int clock);
83 struct radeon_crtc *crtc, unsigned int clock);
501 static void radeon_audio_set_dto(struct drm_encoder *encoder, unsigned int clock) in radeon_audio_set_dto() argument
508 radeon_encoder->audio->set_dto(rdev, crtc, clock); in radeon_audio_set_dto()
559 static void radeon_audio_calc_cts(unsigned int clock, int *CTS, int *N, int freq) in radeon_audio_calc_cts() argument
566 cts = clock * 1000; in radeon_audio_calc_cts()
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H A Datombios_crtc.c564 u32 adjusted_clock = mode->clock; in atombios_adjust_pll()
566 u32 dp_clock = mode->clock; in atombios_adjust_pll()
567 u32 clock = mode->clock; in atombios_adjust_pll() local
569 bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock); in atombios_adjust_pll()
581 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ in atombios_adjust_pll()
595 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000) in atombios_adjust_pll()
600 if (mode->clock > 200000) /* range limits??? */ in atombios_adjust_pll()
641 adjusted_clock = mode->clock * 2; in atombios_adjust_pll()
660 clock = (clock * 5) / 4; in atombios_adjust_pll()
663 clock = (clock * 3) / 2; in atombios_adjust_pll()
[all …]
H A Ddce6_afmt.c282 struct radeon_crtc *crtc, unsigned int clock);
284 struct radeon_crtc *crtc, unsigned int clock) in dce6_hdmi_audio_set_dto() argument
299 WREG32(DCCG_AUDIO_DTO0_MODULE, clock); in dce6_hdmi_audio_set_dto()
303 struct radeon_crtc *crtc, unsigned int clock);
305 struct radeon_crtc *crtc, unsigned int clock) in dce6_dp_audio_set_dto() argument
327 clock = clock * 100 / div; in dce6_dp_audio_set_dto()
330 WREG32(DCE8_DCCG_AUDIO_DTO1_MODULE, clock); in dce6_dp_audio_set_dto()
333 WREG32(DCCG_AUDIO_DTO1_MODULE, clock); in dce6_dp_audio_set_dto()
H A Devergreen_hdmi.c243 struct radeon_crtc *crtc, unsigned int clock);
245 struct radeon_crtc *crtc, unsigned int clock) in dce4_hdmi_audio_set_dto() argument
247 unsigned int max_ratio = clock / 24000; in dce4_hdmi_audio_set_dto()
284 WREG32(DCCG_AUDIO_DTO0_MODULE, clock); in dce4_hdmi_audio_set_dto()
288 struct radeon_crtc *crtc, unsigned int clock);
290 struct radeon_crtc *crtc, unsigned int clock) in dce4_dp_audio_set_dto() argument
318 clock = 100 * clock / div; in dce4_dp_audio_set_dto()
322 WREG32(DCCG_AUDIO_DTO1_MODULE, clock); in dce4_dp_audio_set_dto()
/dflybsd-src/sys/dev/drm/amd/powerplay/hwmgr/
H A Dsmu8_hwmgr.c69 uint32_t clock, uint32_t msg) in smu8_get_eclk_level() argument
79 if (clock <= ptable->entries[i].ecclk) in smu8_get_eclk_level()
87 if (clock >= ptable->entries[i].ecclk) in smu8_get_eclk_level()
100 uint32_t clock, uint32_t msg) in smu8_get_sclk_level() argument
110 if (clock <= table->entries[i].clk) in smu8_get_sclk_level()
118 if (clock >= table->entries[i].clk) in smu8_get_sclk_level()
130 uint32_t clock, uint32_t msg) in smu8_get_uvd_level() argument
140 if (clock <= ptable->entries[i].vclk) in smu8_get_uvd_level()
148 if (clock >= ptable->entries[i].vclk) in smu8_get_uvd_level()
559 unsigned long clock = 0, level; in smu8_init_sclk_limit() local
[all …]
/dflybsd-src/sys/dev/drm/i915/
H A Dintel_dpll_mgr.c553 static unsigned hsw_wrpll_get_budget_for_freq(int clock) in hsw_wrpll_get_budget_for_freq() argument
557 switch (clock) { in hsw_wrpll_get_budget_for_freq()
687 hsw_ddi_calculate_wrpll(int clock /* in Hz */, in hsw_ddi_calculate_wrpll() argument
695 freq2k = clock / 100; in hsw_ddi_calculate_wrpll()
697 budget = hsw_wrpll_get_budget_for_freq(clock); in hsw_ddi_calculate_wrpll()
751 static struct intel_shared_dpll *hsw_ddi_hdmi_get_dpll(int clock, in hsw_ddi_hdmi_get_dpll() argument
759 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p); in hsw_ddi_hdmi_get_dpll()
777 hsw_ddi_dp_get_dpll(struct intel_encoder *encoder, int clock) in hsw_ddi_dp_get_dpll() argument
783 switch (clock / 2) { in hsw_ddi_dp_get_dpll()
794 DRM_DEBUG_KMS("Invalid clock for DP: %d\n", clock); in hsw_ddi_dp_get_dpll()
[all …]
H A Dintel_display.c508 static int pnv_calc_dpll_params(int refclk, struct dpll *clock) in pnv_calc_dpll_params() argument
510 clock->m = clock->m2 + 2; in pnv_calc_dpll_params()
511 clock->p = clock->p1 * clock->p2; in pnv_calc_dpll_params()
512 if (WARN_ON(clock->n == 0 || clock->p == 0)) in pnv_calc_dpll_params()
514 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); in pnv_calc_dpll_params()
515 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); in pnv_calc_dpll_params()
517 return clock->dot; in pnv_calc_dpll_params()
525 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) in i9xx_calc_dpll_params() argument
527 clock->m = i9xx_dpll_compute_m(clock); in i9xx_calc_dpll_params()
528 clock->p = clock->p1 * clock->p2; in i9xx_calc_dpll_params()
[all …]
/dflybsd-src/sys/dev/disk/sdhci/
H A Dsdhci.c81 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock);
176 uint32_t clock; in sdhci_reset() local
187 clock = slot->clock; in sdhci_reset()
188 slot->clock = 0; in sdhci_reset()
189 sdhci_set_clock(slot, clock); in sdhci_reset()
193 slot->clock = 0; in sdhci_reset()
252 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) in sdhci_set_clock() argument
261 if (clock == slot->clock) in sdhci_set_clock()
263 slot->clock = clock; in sdhci_set_clock()
269 if (clock == 0) in sdhci_set_clock()
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/dflybsd-src/share/syscons/keymaps/
H A Dus.emacs.kbd65 058 clock clock clock clock clock clock clock clock O
H A Dru.koi8-r.win.kbd65 058 clock clock clock clock clock clock clock clock O
193 186 clock clock clock clock clock clock clock clock O
H A Del.iso07.kbd111 058 clock clock clock clock clock clock clock clock O
224 186 clock clock clock clock clock clock clock clock O
H A Dru.koi8-r.kbd65 058 alock clock clock clock clock clock clock clock O
193 186 alock clock clock clock clock clock clock clock O
H A Dru.cp866.kbd65 058 alock clock clock clock clock clock clock clock O
194 186 alock clock clock clock clock clock clock clock O
H A Dru.koi8-r.shift.kbd65 058 alock clock clock clock clock clock clock clock O
193 186 alock clock clock clock clock clock clock clock O
H A Dgr.us101.acc.kbd68 058 clock clock clock clock clock clock clock clock O
198 186 clock clock clock clock clock clock clock clock O
H A Dlt.iso4.kbd65 058 clock clock clock clock clock clock clock clock O
193 186 clock clock clock clock clock clock clock clock O
H A Dgr.elot.acc.kbd68 058 clock clock clock clock clock clock clock clock O
198 186 clock clock clock clock clock clock clock clock O
H A Dus.dvorak.kbd5 # esc <-> `~, clock <-> lctrl, and =+ <-> \| (supplied as
74 058 clock clock clock clock clock clock clock clock O
H A Dnorwegian.iso.kbd65 058 clock clock clock clock clock clock clock clock O
/dflybsd-src/sys/dev/drm/
H A Ddrm_modes.c323 tmp -= drm_mode->clock % CVT_CLOCK_STEP; in drm_cvt_mode()
324 drm_mode->clock = tmp; in drm_cvt_mode()
515 drm_mode->clock = pixel_freq; in drm_gtf_mode_complex()
597 dmode->clock = vm->pixelclock / 1000; in drm_display_mode_from_videomode()
637 vm->pixelclock = dmode->clock * 1000; in drm_display_mode_to_videomode()
754 calc_val = (mode->clock * 1000) / mode->htotal; /* hsync in Hz */ in drm_mode_hsync()
781 calc_val = (mode->clock * 1000); in drm_mode_vrefresh()
836 p->crtc_clock = p->clock; in drm_mode_set_crtcinfo()
960 if (mode1->clock && mode2->clock) { in drm_mode_equal()
961 if (KHZ2PICOS(mode1->clock) != KHZ2PICOS(mode2->clock)) in drm_mode_equal()
[all …]
/dflybsd-src/contrib/ldns/
H A Dutil.c275 ldns_gmtime64_r(int64_t clock, struct tm *result) in ldns_gmtime64_r() argument
278 result->tm_sec = (int) LDNS_MOD(clock, 60); in ldns_gmtime64_r()
279 clock = LDNS_DIV(clock, 60); in ldns_gmtime64_r()
280 result->tm_min = (int) LDNS_MOD(clock, 60); in ldns_gmtime64_r()
281 clock = LDNS_DIV(clock, 60); in ldns_gmtime64_r()
282 result->tm_hour = (int) LDNS_MOD(clock, 24); in ldns_gmtime64_r()
283 clock = LDNS_DIV(clock, 24); in ldns_gmtime64_r()
285 ldns_year_and_yday_from_days_since_epoch(clock, result); in ldns_gmtime64_r()

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