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Searched refs:cacheline (Results 1 – 5 of 5) sorted by relevance

/dflybsd-src/sys/dev/drm/i915/
H A Dintel_ringbuffer.h706 #define cacheline(a) round_down(a, CACHELINE_BYTES) in assert_ring_tail_valid() macro
707 GEM_BUG_ON(cacheline(tail) == cacheline(ring->head) && in assert_ring_tail_valid()
709 #undef cacheline in assert_ring_tail_valid()
/dflybsd-src/sys/dev/netif/ti/
H A Dif_ti.c1091 uint32_t cacheline; in ti_chipinit() local
1151 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF; in ti_chipinit()
1160 switch(cacheline) { in ti_chipinit()
1173 cacheline); in ti_chipinit()
/dflybsd-src/contrib/gcc-4.7/gcc/config/i386/
H A Dsync.md128 ;; guarantee for 64-bit accesses that do not cross a cacheline boundary.
/dflybsd-src/contrib/gcc-8.0/gcc/config/i386/
H A Dsync.md136 ;; guarantee for 64-bit accesses that do not cross a cacheline boundary.
H A Di386.opt253 Enum(ix86_align_data) String(cacheline) Value(ix86_align_data_type_cacheline)