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Searched refs:PIPESTAT (Results 1 – 4 of 4) sorted by relevance

/dflybsd-src/sys/dev/drm/i915/
H A Dintel_fifo_underrun.c90 i915_reg_t reg = PIPESTAT(crtc->pipe); in i9xx_check_fifo_underruns()
111 i915_reg_t reg = PIPESTAT(pipe); in i9xx_set_fifo_underrun_reporting()
H A Di915_irq.c618 i915_reg_t reg = PIPESTAT(pipe); in i915_enable_pipestat()
641 i915_reg_t reg = PIPESTAT(pipe); in i915_disable_pipestat()
1796 I915_WRITE(PIPESTAT(pipe), in i9xx_pipestat_irq_reset()
1848 reg = PIPESTAT(pipe); in i9xx_pipestat_irq_ack()
H A Di915_reg.h5437 #define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT) macro
H A Dintel_display.c15429 error->pipe[i].stat = I915_READ(PIPESTAT(i)); in intel_display_capture_error_state()