1 /* $NetBSD: mips3_clockintr.c,v 1.13 2011/12/13 14:23:43 macallan Exp $ */
2
3 /*
4 * Copyright (c) 1988 University of Utah.
5 * Copyright (c) 1992, 1993
6 * The Regents of the University of California. All rights reserved.
7 *
8 * This code is derived from software contributed to Berkeley by
9 * the Systems Programming Group of the University of Utah Computer
10 * Science Department and Ralph Campbell.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 *
36 * from: Utah Hdr: clock.c 1.18 91/01/21
37 *
38 * @(#)clock.c 8.1 (Berkeley) 6/10/93
39 */
40
41 #include <sys/cdefs.h>
42 __KERNEL_RCSID(0, "$NetBSD: mips3_clockintr.c,v 1.13 2011/12/13 14:23:43 macallan Exp $");
43
44 #include <sys/param.h>
45 #include <sys/cpu.h>
46 #include <sys/evcnt.h>
47 #include <sys/intr.h>
48
49 #include <mips/mips3_clock.h>
50
51 #include <mips/locore.h>
52
53 /*
54 * Handling to be done upon receipt of a MIPS 3 clock interrupt. This
55 * routine is to be called from the master interrupt routine
56 * (e.g. cpu_intr), if MIPS INT5 is pending. The caller is
57 * responsible for blocking and renabling the interrupt in the
58 * cpu_intr() routine.
59 */
60
61 static void mips3_init_cp0_clocks(void);
62 void (*initclocks_ptr)(void) = mips3_init_cp0_clocks;
63
64
65 void
mips3_clockintr(struct clockframe * cfp)66 mips3_clockintr(struct clockframe *cfp)
67 {
68 struct cpu_info * const ci = curcpu();
69 uint32_t new_cnt;
70
71 ci->ci_ev_count_compare.ev_count++;
72
73 KASSERT((ci->ci_cycles_per_hz & ~(0xffffffff)) == 0);
74 ci->ci_next_cp0_clk_intr += (uint32_t)(ci->ci_cycles_per_hz & 0xffffffff);
75 mips3_cp0_compare_write(ci->ci_next_cp0_clk_intr);
76
77 /* Check for lost clock interrupts */
78 new_cnt = mips3_cp0_count_read();
79
80 /*
81 * Missed one or more clock interrupts, so let's start
82 * counting again from the current value.
83 */
84 if ((ci->ci_next_cp0_clk_intr - new_cnt) & 0x80000000) {
85
86 ci->ci_next_cp0_clk_intr = new_cnt + curcpu()->ci_cycles_per_hz;
87 mips3_cp0_compare_write(ci->ci_next_cp0_clk_intr);
88 curcpu()->ci_ev_count_compare_missed.ev_count++;
89 }
90
91 /*
92 * Since hardclock is at the end, we can invoke it by a tailcall.
93 */
94
95 hardclock(cfp);
96 /* caller should renable clock interrupts */
97 }
98
99 /*
100 * Start the real-time and statistics clocks. Leave stathz 0 since there
101 * are no other timers available.
102 */
103 static void
mips3_init_cp0_clocks(void)104 mips3_init_cp0_clocks(void)
105 {
106 struct cpu_info * const ci = curcpu();
107
108 ci->ci_next_cp0_clk_intr = mips3_cp0_count_read() + ci->ci_cycles_per_hz;
109 mips3_cp0_compare_write(ci->ci_next_cp0_clk_intr);
110
111 mips3_init_tc();
112
113 }
114
115 void
mips3_initclocks(void)116 mips3_initclocks(void)
117 {
118 if (initclocks_ptr != NULL) {
119 initclocks_ptr();
120 } else {
121 mips3_init_cp0_clocks();
122 }
123
124 /*
125 * Now we can enable all interrupts including hardclock(9)
126 * by CPU INT5.
127 */
128 spl0();
129 }
130
131 /*
132 * We assume newhz is either stathz or profhz, and that neither will
133 * change after being set up above. Could recalculate intervals here
134 * but that would be a drag.
135 */
136 void
mips3_setstatclockrate(int newhz)137 mips3_setstatclockrate(int newhz)
138 {
139
140 /* nothing we can do */
141 }
142
143 __weak_alias(setstatclockrate, mips3_setstatclockrate);
144 __weak_alias(cpu_initclocks, mips3_initclocks);
145