1 /* $NetBSD: soc15.h,v 1.2 2021/12/18 23:44:59 riastradh Exp $ */ 2 3 /* 4 * Copyright 2016 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #ifndef __SOC15_H__ 27 #define __SOC15_H__ 28 29 #include "nbio_v6_1.h" 30 #include "nbio_v7_0.h" 31 #include "nbio_v7_4.h" 32 33 #define SOC15_FLUSH_GPU_TLB_NUM_WREG 6 34 #define SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT 3 35 36 extern const struct amd_ip_funcs soc15_common_ip_funcs; 37 38 struct soc15_reg_golden { 39 u32 hwip; 40 u32 instance; 41 u32 segment; 42 u32 reg; 43 u32 and_mask; 44 u32 or_mask; 45 }; 46 47 struct soc15_reg_entry { 48 uint32_t hwip; 49 uint32_t inst; 50 uint32_t seg; 51 uint32_t reg_offset; 52 uint32_t reg_value; 53 uint32_t se_num; 54 uint32_t instance; 55 }; 56 57 struct soc15_allowed_register_entry { 58 uint32_t hwip; 59 uint32_t inst; 60 uint32_t seg; 61 uint32_t reg_offset; 62 bool grbm_indexed; 63 }; 64 65 struct soc15_ras_field_entry { 66 const char *name; 67 uint32_t hwip; 68 uint32_t inst; 69 uint32_t seg; 70 uint32_t reg_offset; 71 uint32_t sec_count_mask; 72 uint32_t sec_count_shift; 73 uint32_t ded_count_mask; 74 uint32_t ded_count_shift; 75 }; 76 77 #define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst, reg##_BASE_IDX, reg 78 79 #define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset) 80 81 #define SOC15_REG_GOLDEN_VALUE(ip, inst, reg, and_mask, or_mask) \ 82 { ip##_HWIP, inst, reg##_BASE_IDX, reg, and_mask, or_mask } 83 84 #define SOC15_REG_FIELD(reg, field) reg##__##field##_MASK, reg##__##field##__SHIFT 85 86 void soc15_grbm_select(struct amdgpu_device *adev, 87 u32 me, u32 pipe, u32 queue, u32 vmid); 88 int soc15_set_ip_blocks(struct amdgpu_device *adev); 89 90 void soc15_program_register_sequence(struct amdgpu_device *adev, 91 const struct soc15_reg_golden *registers, 92 const u32 array_size); 93 94 int vega10_reg_base_init(struct amdgpu_device *adev); 95 int vega20_reg_base_init(struct amdgpu_device *adev); 96 int arct_reg_base_init(struct amdgpu_device *adev); 97 98 void vega10_doorbell_index_init(struct amdgpu_device *adev); 99 void vega20_doorbell_index_init(struct amdgpu_device *adev); 100 #endif 101