xref: /netbsd-src/external/gpl3/gdb/dist/sim/testsuite/bfin/c_progctrl_clisti_interr.S (revision 4b169a6ba595ae283ca507b26b15fdff40495b1c) 
1//Original:/proj/frio/dv/testcases/core/c_progctrl_clisti_interr/c_progctrl_clisti_interr.dsp
2// Spec Reference: CLI STI interrupt on HW TIMER
3# mach: bfin
4# sim: --environment operating
5
6#include "test.h"
7.include "testutils.inc"
8start
9
10//
11// Include Files
12//
13
14include(std.inc)
15include(selfcheck.inc)
16
17// Defines
18
19#ifndef TCNTL
20#define TCNTL            0xFFE03000
21#endif
22#ifndef TPERIOD
23#define TPERIOD          0xFFE03004
24#endif
25#ifndef TSCALE
26#define TSCALE           0xFFE03008
27#endif
28#ifndef TCOUNT
29#define TCOUNT           0xFFE0300c
30#endif
31#ifndef EVT
32#define EVT              0xFFE02000
33#endif
34#ifndef EVT15
35#define EVT15            0xFFE0203c
36#endif
37#ifndef EVT_OVERRIDE
38#define EVT_OVERRIDE     0xFFE02100
39#endif
40#ifndef ITABLE
41#define ITABLE           0x000FF000
42#endif
43#ifndef PROGRAM_STACK
44#define PROGRAM_STACK    0x000FF100
45#endif
46#ifndef STACKSIZE
47#define STACKSIZE        0x00000300
48#endif
49
50// Boot code
51
52
53INIT_R_REGS(0);                             // Initialize Dregs
54INIT_P_REGS(0);                             // Initialize Pregs
55
56      //CHECK_INIT(p5,   0xE0000000);
57include(symtable.inc)
58CHECK_INIT_DEF(p5);
59 BOOT :
60
61LD32(sp, 0x000FF200);
62LD32(p0, EVT);              // Setup Event Vectors and Handlers
63
64LD32_LABEL(r0, EHANDLE);    // Emulation Handler (Int0)
65        [ P0 ++ ] = R0;
66
67LD32_LABEL(r0, RHANDLE);    // Reset Handler (Int1)
68        [ P0 ++ ] = R0;
69
70LD32_LABEL(r0, NHANDLE);    // NMI Handler (Int2)
71        [ P0 ++ ] = R0;
72
73LD32_LABEL(r0, XHANDLE);    // Exception Handler (Int3)
74        [ P0 ++ ] = R0;
75
76        [ P0 ++ ] = R0;                // IVT4 not used
77
78LD32_LABEL(r0, HWHANDLE);   // HW Error Handler (Int5)
79        [ P0 ++ ] = R0;
80
81LD32_LABEL(r0, THANDLE);    // Timer Handler (Int6)
82        [ P0 ++ ] = R0;
83
84LD32_LABEL(r0, I7HANDLE);   // IVG7 Handler
85        [ P0 ++ ] = R0;
86
87LD32_LABEL(r0, I8HANDLE);   // IVG8 Handler
88        [ P0 ++ ] = R0;
89
90LD32_LABEL(r0, I9HANDLE);   // IVG9 Handler
91        [ P0 ++ ] = R0;
92
93LD32_LABEL(r0, I10HANDLE);  // IVG10 Handler
94        [ P0 ++ ] = R0;
95
96LD32_LABEL(r0, I11HANDLE);  // IVG11 Handler
97        [ P0 ++ ] = R0;
98
99LD32_LABEL(r0, I12HANDLE);  // IVG12 Handler
100        [ P0 ++ ] = R0;
101
102LD32_LABEL(r0, I13HANDLE);  // IVG13 Handler
103        [ P0 ++ ] = R0;
104
105LD32_LABEL(r0, I14HANDLE);  // IVG14 Handler
106        [ P0 ++ ] = R0;
107
108LD32_LABEL(r0, I15HANDLE);  // IVG15 Handler
109        [ P0 ++ ] = R0;
110
111LD32(p0, EVT_OVERRIDE);
112        R0 = 0;
113        [ P0 ++ ] = R0;
114        R0 = -1;     // Change this to mask interrupts (*)
115        [ P0 ] = R0;   // IMASK
116
117LD32_LABEL(p1, START);
118
119LD32(p0, EVT15);
120        [ P0 ] = P1;   // IVG15 (General) handler (Int 15) load with start
121
122RAISE 15;    // after we RTI, INT 15 should be taken
123
124LD32_LABEL(r7, START);
125RETI = r7;
126NOP;        // Workaround for Bug 217
127RTI;
128NOP;
129NOP;
130NOP;
131NOP;
132NOP;
133NOP;
134NOP;
135NOP;
136DUMMY:
137	  NOP;
138NOP;
139NOP;
140NOP;
141NOP;
142NOP;
143NOP;
144NOP;
145NOP;
146NOP;
147
148 START :
149        R7 = 0x0;
150        R6 = 0x1;
151        [ -- SP ] = RETI;        // Enable Nested Interrupts
152
153CLI R1;                                           // stop interrupt
154WR_MMR(TCNTL,   0x00000001, p0, r0);        // Turn ON TMPWR (active state)
155WR_MMR(TPERIOD, 0x00000050, p0, r0);
156WR_MMR(TCOUNT,  0x00000013, p0, r0);
157WR_MMR(TSCALE,  0x00000000, p0, r0);
158CSYNC;
159        // Read the contents of the Timer
160
161RD_MMR(TPERIOD, p0, r2);
162CHECKREG(r2,    0x00000050);
163
164//      RD_MMR(TCOUNT, p0, r3);
165//      CHECKREG(r3, 0x00000013);// fsim -ro useChecker=regtrace -seed 8b8db910
166
167
168WR_MMR(TCNTL,   0x00000003, p0, r0);        // enable Timer (TMPWR, TMREN)
169CSYNC;
170
171NOP; NOP; NOP;
172NOP; NOP; NOP;
173NOP; NOP; NOP;
174NOP; NOP; NOP;
175NOP; NOP; NOP;
176NOP; NOP; NOP;
177NOP; NOP; NOP;
178NOP; NOP; NOP;
179RD_MMR(TPERIOD, p0, r4);
180CHECKREG(r4,    0x00000050);
181
182//      RD_MMR(TCNTL, p0, r5);
183//      CHECKREG(r5,    0x0000000B);                // INTERRUPT did happen
184
185WR_MMR(TCNTL,   0x00000000, p0, r0);        // Turn OFF Timer
186CSYNC;
187NOP;
188WR_MMR(TCNTL,   0x00000001, p0, r0);        // Turn ON Timer Power
189WR_MMR(TPERIOD, 0x00000015, p0, r0);
190WR_MMR(TCOUNT,  0x00000013, p0, r0);
191WR_MMR(TSCALE,  0x00000002, p0, r0);
192WR_MMR(TCNTL,   0x00000007, p0, r0);        // Turn ON Timer (TAUTORLD=1)
193CSYNC;
194NOP;
195NOP;
196NOP;
197NOP;
198NOP;
199NOP;
200NOP;
201NOP;
202NOP;
203NOP;
204NOP;
205NOP;
206NOP;
207NOP;
208NOP;
209JUMP.S label4;
210        R4.L = 0x1111;                             // Will be killed
211        R4.H = 0x1111;                             // Will be killed
212NOP;
213NOP;
214NOP;
215label5: R5.H = 0x7777;
216        R5.L = 0x7888;
217JUMP.S label6;
218        R5.L = 0x1111;                             // Will be killed
219        R5.H = 0x1111;                             // Will be killed
220NOP;
221NOP;
222NOP;
223NOP;
224NOP;
225NOP;
226label4: R4.H = 0x5555;
227        R4.L = 0x6666;
228NOP;
229JUMP.S label5;
230        R5.L = 0x2222;     // Will be killed
231        R5.H = 0x2222;     // Will be killed
232NOP;
233NOP;
234NOP;
235NOP;
236label6: R3.H = 0x7999;
237        R3.L = 0x7aaa;
238NOP;
239NOP;
240NOP;
241NOP;
242NOP;
243NOP;
244NOP;
245                                                    // With auto reload
246        // Read the contents of the Timer
247
248RD_MMR(TPERIOD, p0, r2);
249CHECKREG(r2,    0x00000015);
250
251//      RD_MMR(TCNTL , p0, r3);
252//      CHECKREG(r3,    0x0000000F);
253NOP;
254CHECKREG(r7,    0x00000000);    // no interrupt being serviced
255NOP;
256STI R1;
257
258NOP; NOP; NOP;
259NOP; NOP; NOP;
260WR_MMR(TCNTL,   0x00000000, p0, r0);        // Turn OFF Timer
261CSYNC;
262NOP; NOP; NOP;
263
264
265
266
267
268dbg_pass;        // Call Endtest Macro
269
270
271
272//*********************************************************************
273//
274// Handlers for Events
275//
276
277EHANDLE:            // Emulation Handler 0
278RTE;
279
280RHANDLE:            // Reset Handler 1
281RTI;
282
283NHANDLE:            // NMI Handler 2
284RTN;
285
286XHANDLE:            // Exception Handler 3
287RTX;
288
289HWHANDLE:           // HW Error Handler 5
290RTI;
291
292THANDLE:            // Timer Handler 6
293        R7 = R7 + R6;
294RTI;
295
296I7HANDLE:           // IVG 7 Handler
297RTI;
298
299I8HANDLE:           // IVG 8 Handler
300RTI;
301
302I9HANDLE:           // IVG 9 Handler
303RTI;
304
305I10HANDLE:          // IVG 10 Handler
306RTI;
307
308I11HANDLE:          // IVG 11 Handler
309RTI;
310
311I12HANDLE:          // IVG 12 Handler
312RTI;
313
314I13HANDLE:          // IVG 13 Handler
315RTI;
316
317I14HANDLE:          // IVG 14 Handler
318RTI;
319
320I15HANDLE:          // IVG 15 Handler
321        R5 = RETI;
322        P0 = R5;
323JUMP ( P0 );
324RTI;
325
326.section MEM_PROGRAM_STACK,"aw"
327
328.space (STACKSIZE);
329STACK:
330NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
331