1 /* SPDX-License-Identifier: BSD-3-Clause
2 *
3 * Copyright(c) 2019-2021 Xilinx, Inc.
4 * Copyright(c) 2018-2019 Solarflare Communications Inc.
5 *
6 * This software was jointly developed between OKTET Labs (under contract
7 * for Solarflare) and Solarflare Communications, Inc.
8 */
9
10 #ifndef _SFC_EF10_RX_EV_H
11 #define _SFC_EF10_RX_EV_H
12
13 #include <rte_mbuf.h>
14
15 #include "efx_types.h"
16 #include "efx_regs.h"
17 #include "efx_regs_ef10.h"
18
19 #include "sfc_debug.h"
20
21 #ifdef __cplusplus
22 extern "C" {
23 #endif
24
25 static inline void
sfc_ef10_rx_ev_to_offloads(const efx_qword_t rx_ev,struct rte_mbuf * m,uint64_t ol_mask)26 sfc_ef10_rx_ev_to_offloads(const efx_qword_t rx_ev, struct rte_mbuf *m,
27 uint64_t ol_mask)
28 {
29 uint32_t tun_ptype = 0;
30 /* Which event bit is mapped to RTE_MBUF_F_RX_IP_CKSUM_* */
31 int8_t ip_csum_err_bit;
32 /* Which event bit is mapped to RTE_MBUF_F_RX_L4_CKSUM_* */
33 int8_t l4_csum_err_bit;
34 uint32_t l2_ptype = 0;
35 uint32_t l3_ptype = 0;
36 uint32_t l4_ptype = 0;
37 uint64_t ol_flags = 0;
38
39 if (unlikely(rx_ev.eq_u64[0] &
40 rte_cpu_to_le_64((1ull << ESF_DZ_RX_ECC_ERR_LBN) |
41 (1ull << ESF_DZ_RX_ECRC_ERR_LBN) |
42 (1ull << ESF_DZ_RX_PARSE_INCOMPLETE_LBN)))) {
43 /* Zero packet type is used as a marker to discard bad packets */
44 goto done;
45 }
46
47 #if SFC_EF10_RX_EV_ENCAP_SUPPORT
48 switch (EFX_QWORD_FIELD(rx_ev, ESF_EZ_RX_ENCAP_HDR)) {
49 default:
50 /* Unexpected encapsulation tag class */
51 SFC_ASSERT(false);
52 /* FALLTHROUGH */
53 case ESE_EZ_ENCAP_HDR_NONE:
54 break;
55 case ESE_EZ_ENCAP_HDR_VXLAN:
56 /*
57 * It is definitely UDP, but we have no information
58 * about IPv4 vs IPv6 and VLAN tagging.
59 */
60 tun_ptype = RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L4_UDP;
61 break;
62 case ESE_EZ_ENCAP_HDR_GRE:
63 /*
64 * We have no information about IPv4 vs IPv6 and VLAN tagging.
65 */
66 tun_ptype = RTE_PTYPE_TUNNEL_NVGRE;
67 break;
68 }
69 #endif
70
71 if (tun_ptype == 0) {
72 ip_csum_err_bit = ESF_DZ_RX_IPCKSUM_ERR_LBN;
73 l4_csum_err_bit = ESF_DZ_RX_TCPUDP_CKSUM_ERR_LBN;
74 } else {
75 ip_csum_err_bit = ESF_EZ_RX_IP_INNER_CHKSUM_ERR_LBN;
76 l4_csum_err_bit = ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR_LBN;
77 if (unlikely(EFX_TEST_QWORD_BIT(rx_ev,
78 ESF_DZ_RX_IPCKSUM_ERR_LBN)))
79 ol_flags |= RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD;
80 }
81
82 switch (EFX_QWORD_FIELD(rx_ev, ESF_DZ_RX_ETH_TAG_CLASS)) {
83 case ESE_DZ_ETH_TAG_CLASS_NONE:
84 l2_ptype = (tun_ptype == 0) ? RTE_PTYPE_L2_ETHER :
85 RTE_PTYPE_INNER_L2_ETHER;
86 break;
87 case ESE_DZ_ETH_TAG_CLASS_VLAN1:
88 l2_ptype = (tun_ptype == 0) ? RTE_PTYPE_L2_ETHER_VLAN :
89 RTE_PTYPE_INNER_L2_ETHER_VLAN;
90 break;
91 case ESE_DZ_ETH_TAG_CLASS_VLAN2:
92 l2_ptype = (tun_ptype == 0) ? RTE_PTYPE_L2_ETHER_QINQ :
93 RTE_PTYPE_INNER_L2_ETHER_QINQ;
94 break;
95 default:
96 /* Unexpected Eth tag class */
97 SFC_ASSERT(false);
98 }
99
100 switch (EFX_QWORD_FIELD(rx_ev, ESF_DZ_RX_L3_CLASS)) {
101 case ESE_DZ_L3_CLASS_IP4_FRAG:
102 l4_ptype = (tun_ptype == 0) ? RTE_PTYPE_L4_FRAG :
103 RTE_PTYPE_INNER_L4_FRAG;
104 /* FALLTHROUGH */
105 case ESE_DZ_L3_CLASS_IP4:
106 l3_ptype = (tun_ptype == 0) ? RTE_PTYPE_L3_IPV4_EXT_UNKNOWN :
107 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
108 ol_flags |= RTE_MBUF_F_RX_RSS_HASH |
109 ((EFX_TEST_QWORD_BIT(rx_ev, ip_csum_err_bit)) ?
110 RTE_MBUF_F_RX_IP_CKSUM_BAD : RTE_MBUF_F_RX_IP_CKSUM_GOOD);
111 break;
112 case ESE_DZ_L3_CLASS_IP6_FRAG:
113 l4_ptype = (tun_ptype == 0) ? RTE_PTYPE_L4_FRAG :
114 RTE_PTYPE_INNER_L4_FRAG;
115 /* FALLTHROUGH */
116 case ESE_DZ_L3_CLASS_IP6:
117 l3_ptype = (tun_ptype == 0) ? RTE_PTYPE_L3_IPV6_EXT_UNKNOWN :
118 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
119 ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
120 break;
121 case ESE_DZ_L3_CLASS_ARP:
122 /* Override Layer 2 packet type */
123 /* There is no ARP classification for inner packets */
124 if (tun_ptype == 0)
125 l2_ptype = RTE_PTYPE_L2_ETHER_ARP;
126 break;
127 case ESE_DZ_L3_CLASS_UNKNOWN:
128 break;
129 default:
130 /* Unexpected Layer 3 class */
131 SFC_ASSERT(false);
132 }
133
134 /*
135 * RX_L4_CLASS is 3 bits wide on Huntington and Medford, but is only
136 * 2 bits wide on Medford2. Check it is safe to use the Medford2 field
137 * and values for all EF10 controllers.
138 */
139 RTE_BUILD_BUG_ON(ESF_FZ_RX_L4_CLASS_LBN != ESF_DE_RX_L4_CLASS_LBN);
140 switch (EFX_QWORD_FIELD(rx_ev, ESF_FZ_RX_L4_CLASS)) {
141 case ESE_FZ_L4_CLASS_TCP:
142 RTE_BUILD_BUG_ON(ESE_FZ_L4_CLASS_TCP != ESE_DE_L4_CLASS_TCP);
143 l4_ptype = (tun_ptype == 0) ? RTE_PTYPE_L4_TCP :
144 RTE_PTYPE_INNER_L4_TCP;
145 ol_flags |=
146 (EFX_TEST_QWORD_BIT(rx_ev, l4_csum_err_bit)) ?
147 RTE_MBUF_F_RX_L4_CKSUM_BAD : RTE_MBUF_F_RX_L4_CKSUM_GOOD;
148 break;
149 case ESE_FZ_L4_CLASS_UDP:
150 RTE_BUILD_BUG_ON(ESE_FZ_L4_CLASS_UDP != ESE_DE_L4_CLASS_UDP);
151 l4_ptype = (tun_ptype == 0) ? RTE_PTYPE_L4_UDP :
152 RTE_PTYPE_INNER_L4_UDP;
153 ol_flags |=
154 (EFX_TEST_QWORD_BIT(rx_ev, l4_csum_err_bit)) ?
155 RTE_MBUF_F_RX_L4_CKSUM_BAD : RTE_MBUF_F_RX_L4_CKSUM_GOOD;
156 break;
157 case ESE_FZ_L4_CLASS_UNKNOWN:
158 RTE_BUILD_BUG_ON(ESE_FZ_L4_CLASS_UNKNOWN !=
159 ESE_DE_L4_CLASS_UNKNOWN);
160 break;
161 default:
162 /* Unexpected Layer 4 class */
163 SFC_ASSERT(false);
164 }
165
166 SFC_ASSERT(l2_ptype != 0);
167
168 done:
169 m->ol_flags = ol_flags & ol_mask;
170 m->packet_type = tun_ptype | l2_ptype | l3_ptype | l4_ptype;
171 }
172
173
174 #ifdef __cplusplus
175 }
176 #endif
177 #endif /* _SFC_EF10_RX_EV_H */
178