1 /* $NetBSD: schizo.c,v 1.47 2022/01/21 19:14:14 thorpej Exp $ */
2 /* $OpenBSD: schizo.c,v 1.55 2008/08/18 20:29:37 brad Exp $ */
3
4 /*
5 * Copyright (c) 2002 Jason L. Wright (jason@thought.net)
6 * Copyright (c) 2003 Henric Jungheim
7 * Copyright (c) 2008, 2009, 2010, 2012 Matthew R. Green
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include <sys/cdefs.h>
33 __KERNEL_RCSID(0, "$NetBSD: schizo.c,v 1.47 2022/01/21 19:14:14 thorpej Exp $");
34
35 #include <sys/param.h>
36 #include <sys/device.h>
37 #include <sys/errno.h>
38 #include <sys/extent.h>
39 #include <sys/kmem.h>
40 #include <sys/malloc.h>
41 #include <sys/systm.h>
42 #include <sys/time.h>
43 #include <sys/reboot.h>
44
45 #define _SPARC_BUS_DMA_PRIVATE
46 #include <sys/bus.h>
47 #include <machine/autoconf.h>
48 #include <machine/psl.h>
49
50 #include <dev/pci/pcivar.h>
51 #include <dev/pci/pcireg.h>
52
53 #include <sparc64/dev/iommureg.h>
54 #include <sparc64/dev/iommuvar.h>
55 #include <sparc64/dev/schizoreg.h>
56 #include <sparc64/dev/schizovar.h>
57 #include <sparc64/sparc64/cache.h>
58
59 #ifdef DEBUG
60 #define SDB_PROM 0x01
61 #define SDB_BUSMAP 0x02
62 #define SDB_INTR 0x04
63 #define SDB_INTMAP 0x08
64 #define SDB_CONF 0x10
65 int schizo_debug = 0x0;
66 #define DPRINTF(l, s) do { if (schizo_debug & l) printf s; } while (0)
67 #else
68 #define DPRINTF(l, s)
69 #endif
70
71 extern struct sparc_pci_chipset _sparc_pci_chipset;
72
73 static int schizo_match(device_t, cfdata_t, void *);
74 static void schizo_attach(device_t, device_t, void *);
75 static int schizo_print(void *aux, const char *p);
76
77 #ifdef DEBUG
78 void schizo_print_regs(int unit, int what);
79 #endif
80
81 CFATTACH_DECL_NEW(schizo, sizeof(struct schizo_softc),
82 schizo_match, schizo_attach, NULL, NULL);
83
84 void schizo_init_iommu(struct schizo_softc *, struct schizo_pbm *);
85
86 void schizo_set_intr(struct schizo_softc *, struct schizo_pbm *, int,
87 int (*handler)(void *), void *, int, const char *);
88 int schizo_ue(void *);
89 int schizo_ce(void *);
90 int schizo_safari_error(void *);
91 int schizo_pci_error(void *);
92
93 pci_chipset_tag_t schizo_alloc_chipset(struct schizo_pbm *, int,
94 pci_chipset_tag_t);
95 bus_space_tag_t schizo_alloc_mem_tag(struct schizo_pbm *);
96 bus_space_tag_t schizo_alloc_io_tag(struct schizo_pbm *);
97 bus_space_tag_t schizo_alloc_config_tag(struct schizo_pbm *);
98 bus_space_tag_t schizo_alloc_bus_tag(struct schizo_pbm *, const char *,
99 int);
100 bus_dma_tag_t schizo_alloc_dma_tag(struct schizo_pbm *);
101
102 pcireg_t schizo_conf_read(pci_chipset_tag_t, pcitag_t, int);
103 void schizo_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t);
104
105 int schizo_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size,
106 int flags, vaddr_t unused, bus_space_handle_t *hp);
107 static paddr_t schizo_bus_mmap(bus_space_tag_t t, bus_addr_t paddr,
108 off_t off, int prot, int flags);
109 static void *schizo_intr_establish(bus_space_tag_t, int, int, int (*)(void *),
110 void *, void(*)(void));
111 static int schizo_pci_intr_map(const struct pci_attach_args *,
112 pci_intr_handle_t *);
113 static void *schizo_pci_intr_establish(pci_chipset_tag_t, pci_intr_handle_t,
114 int, int (*)(void *), void *);
115 static int schizo_dmamap_create(bus_dma_tag_t, bus_size_t, int, bus_size_t,
116 bus_size_t, int, bus_dmamap_t *);
117
118 int
schizo_match(device_t parent,cfdata_t match,void * aux)119 schizo_match(device_t parent, cfdata_t match, void *aux)
120 {
121 struct mainbus_attach_args *ma = aux;
122 char *str;
123
124 if (strcmp(ma->ma_name, "pci") != 0)
125 return (0);
126
127 str = prom_getpropstring(ma->ma_node, "model");
128 if (strcmp(str, "schizo") == 0)
129 return (1);
130
131 str = prom_getpropstring(ma->ma_node, "compatible");
132 if (strcmp(str, "pci108e,8001") == 0)
133 return (1);
134 if (strcmp(str, "pci108e,8002") == 0) /* XMITS */
135 return (1);
136 if (strcmp(str, "pci108e,a801") == 0) /* Tomatillo */
137 return (1);
138
139 return (0);
140 }
141
142 void
schizo_attach(device_t parent,device_t self,void * aux)143 schizo_attach(device_t parent, device_t self, void *aux)
144 {
145 struct schizo_softc *sc = device_private(self);
146 struct mainbus_attach_args *ma = aux;
147 struct schizo_pbm *pbm;
148 struct iommu_state *is;
149 struct pcibus_attach_args pba;
150 uint64_t reg, eccctrl, ino_bitmap;
151 int *busranges = NULL, nranges, *ino_bitmaps = NULL, nbitmaps;
152 char *str;
153 bool no_sc;
154
155 aprint_normal(": addr %" PRIx64, ma->ma_reg[0].ur_paddr);
156 str = prom_getpropstring(ma->ma_node, "compatible");
157 if (strcmp(str, "pci108e,a801") == 0)
158 sc->sc_tomatillo = 1;
159
160 sc->sc_dev = self;
161 sc->sc_node = ma->ma_node;
162 sc->sc_dmat = ma->ma_dmatag;
163 sc->sc_bustag = ma->ma_bustag;
164
165 sc->sc_ver = prom_getpropint(sc->sc_node, "version#", 0);
166
167 if (bus_space_map(sc->sc_bustag, ma->ma_reg[1].ur_paddr - 0x10000UL,
168 sizeof(struct schizo_regs), 0,
169 &sc->sc_ctrlh)) {
170 aprint_error(": failed to map registers\n");
171 return;
172 }
173
174 sc->sc_ign = INTIGN(ma->ma_upaid << INTMAP_IGN_SHIFT);
175
176 /* enable schizo ecc error interrupts */
177 eccctrl = schizo_read(sc, SCZ_ECCCTRL);
178 eccctrl |= SCZ_ECCCTRL_EE_INTEN |
179 SCZ_ECCCTRL_UE_INTEN |
180 SCZ_ECCCTRL_CE_INTEN;
181 schizo_write(sc, SCZ_ECCCTRL, eccctrl);
182
183 pbm = kmem_zalloc(sizeof(*pbm), KM_SLEEP);
184 #ifdef DEBUG
185 sc->sc_pbm = pbm;
186 #endif
187 pbm->sp_sc = sc;
188 pbm->sp_regt = sc->sc_bustag;
189
190 if ((ma->ma_reg[0].ur_paddr & 0x00700000) == 0x00600000)
191 pbm->sp_bus_a = 1;
192 else
193 pbm->sp_bus_a = 0;
194
195 /*
196 * Map interrupt registers
197 */
198 if (bus_space_map(sc->sc_bustag, ma->ma_reg[0].ur_paddr,
199 ma->ma_reg[0].ur_len,
200 BUS_SPACE_MAP_LINEAR, &pbm->sp_intrh)) {
201 aprint_error(": failed to map interrupt registers\n");
202 kmem_free(pbm, sizeof(*pbm));
203 return;
204 }
205
206 #ifdef DEBUG
207 /*
208 * Map ichip registers
209 */
210 if (sc->sc_tomatillo)
211 if (bus_space_map(sc->sc_bustag, ma->ma_reg[3].ur_paddr,
212 ma->ma_reg[3].ur_len,
213 BUS_SPACE_MAP_LINEAR, &pbm->sp_ichiph)) {
214 aprint_error(": failed to map ichip registers\n");
215 kmem_free(pbm, sizeof(*pbm));
216 return;
217 }
218 #endif
219
220 if (prom_getprop(sc->sc_node, "ranges", sizeof(struct schizo_range),
221 &pbm->sp_nrange, (void **)&pbm->sp_range))
222 panic("schizo: can't get ranges");
223
224 if (prom_getprop(sc->sc_node, "bus-range", sizeof(int), &nranges,
225 (void **)&busranges))
226 panic("schizo: can't get bus-range");
227
228 aprint_normal(": %s, version %d, ign %x, bus %c %d to %d\n",
229 sc->sc_tomatillo ? "Tomatillo" : "Schizo", sc->sc_ver,
230 sc->sc_ign, pbm->sp_bus_a ? 'A' : 'B', busranges[0], busranges[1]);
231 aprint_naive("\n");
232
233 if (bus_space_subregion(pbm->sp_regt, sc->sc_ctrlh,
234 pbm->sp_bus_a ? offsetof(struct schizo_regs, pbm_a) :
235 offsetof(struct schizo_regs, pbm_b),
236 sizeof(struct schizo_pbm_regs),
237 &pbm->sp_regh)) {
238 panic("schizo: unable to create PBM handle");
239 }
240
241 is = &pbm->sp_is;
242 pbm->sp_sb.sb_is = is;
243 no_sc = prom_getproplen(sc->sc_node, "no-streaming-cache") >= 0;
244 if (no_sc)
245 aprint_debug_dev(sc->sc_dev, "no streaming buffers\n");
246 else {
247 vaddr_t va = (vaddr_t)&pbm->sp_flush[0x40];
248
249 /*
250 * Initialize the strbuf_ctl.
251 *
252 * The flush sync buffer must be 64-byte aligned.
253 */
254 is->is_sb[0] = &pbm->sp_sb;
255 is->is_sb[0]->sb_flush = (void *)(va & ~0x3f);
256
257 bus_space_subregion(pbm->sp_regt, pbm->sp_regh,
258 offsetof(struct schizo_pbm_regs, strbuf),
259 sizeof(struct iommu_strbuf), &is->is_sb[0]->sb_sb);
260 }
261
262 aprint_normal_dev(sc->sc_dev, " ");
263 if (sc->sc_tomatillo)
264 is->is_flags |= IOMMU_SYNC_BEFORE_UNMAP;
265 schizo_init_iommu(sc, pbm);
266
267 pbm->sp_memt = schizo_alloc_mem_tag(pbm);
268 pbm->sp_iot = schizo_alloc_io_tag(pbm);
269 pbm->sp_cfgt = schizo_alloc_config_tag(pbm);
270 pbm->sp_dmat = schizo_alloc_dma_tag(pbm);
271 pbm->sp_flags = (pbm->sp_memt ? PCI_FLAGS_MEM_OKAY : 0) |
272 (pbm->sp_iot ? PCI_FLAGS_IO_OKAY : 0);
273
274 if (bus_space_map(pbm->sp_cfgt, 0, 0x1000000, 0, &pbm->sp_cfgh))
275 panic("schizo: could not map config space");
276
277 pbm->sp_pc = schizo_alloc_chipset(pbm, sc->sc_node,
278 &_sparc_pci_chipset);
279 pbm->sp_pc->spc_busmax = busranges[1];
280 pbm->sp_pc->spc_busnode = kmem_zalloc(sizeof(*pbm->sp_pc->spc_busnode),
281 KM_SLEEP);
282
283 pba.pba_bus = busranges[0];
284 pba.pba_bridgetag = NULL;
285 pba.pba_pc = pbm->sp_pc;
286 pba.pba_flags = pbm->sp_flags;
287 pba.pba_dmat = pbm->sp_dmat;
288 pba.pba_dmat64 = NULL; /* XXX */
289 pba.pba_memt = pbm->sp_memt;
290 pba.pba_iot = pbm->sp_iot;
291
292 free(busranges, M_DEVBUF);
293
294 schizo_pbm_write(pbm, SCZ_PCI_INTR_RETRY, 5);
295
296 /* clear out the bus errors */
297 schizo_pbm_write(pbm, SCZ_PCI_CTRL, schizo_pbm_read(pbm, SCZ_PCI_CTRL));
298 schizo_pbm_write(pbm, SCZ_PCI_AFSR, schizo_pbm_read(pbm, SCZ_PCI_AFSR));
299 schizo_cfg_write(pbm, PCI_COMMAND_STATUS_REG,
300 schizo_cfg_read(pbm, PCI_COMMAND_STATUS_REG));
301
302 reg = schizo_pbm_read(pbm, SCZ_PCI_CTRL);
303 /* enable/disable error interrupts and arbiter */
304 reg |= SCZ_PCICTRL_EEN | SCZ_PCICTRL_MMU_INT;
305 if (sc->sc_tomatillo) {
306 reg &= ~SCZ_PCICTRL_SBH_INT;
307 reg |= TOM_PCICTRL_ARB;
308 reg |= TOM_PCICTRL_PRM | TOM_PCICTRL_PRO |
309 TOM_PCICTRL_PRL;
310 if (sc->sc_ver <= 1) /* 2.0 */
311 reg |= TOM_PCICTRL_DTO_INT;
312 else
313 reg |= SCZ_PCICTRL_PTO;
314 } else
315 reg |= SCZ_PCICTRL_SBH_INT | SCZ_PCICTRL_ARB;
316 if (OF_getproplen(sc->sc_node, "no-bus-parking") < 0)
317 reg |= SCZ_PCICTRL_PARK;
318 schizo_pbm_write(pbm, SCZ_PCI_CTRL, reg);
319
320 reg = schizo_pbm_read(pbm, SCZ_PCI_DIAG);
321 reg &= ~(SCZ_PCIDIAG_D_RTRYARB | SCZ_PCIDIAG_D_RETRY |
322 SCZ_PCIDIAG_D_INTSYNC);
323 schizo_pbm_write(pbm, SCZ_PCI_DIAG, reg);
324
325 if (prom_getprop(sc->sc_node, "ino-bitmap", sizeof(int), &nbitmaps,
326 (void **)&ino_bitmaps)) {
327 /* No property - set defaults (double map UE, CE, SERR). */
328 if (pbm->sp_bus_a)
329 ino_bitmap = __BIT(SCZ_PCIERR_A_INO);
330 else
331 ino_bitmap = __BIT(SCZ_PCIERR_B_INO);
332 ino_bitmap |= __BIT(SCZ_UE_INO) | __BIT(SCZ_CE_INO) |
333 __BIT(SCZ_SERR_INO);
334 } else
335 ino_bitmap = (uint64_t) ino_bitmaps[1] << 32 | ino_bitmaps[0];
336 DPRINTF(SDB_INTR, ("ino_bitmap=0x%016" PRIx64 "\n", ino_bitmap));
337
338 if (ino_bitmap & __BIT(SCZ_PCIERR_A_INO))
339 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_pci_error,
340 pbm, SCZ_PCIERR_A_INO, "pci_a");
341 if (ino_bitmap & __BIT(SCZ_PCIERR_B_INO))
342 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_pci_error,
343 pbm, SCZ_PCIERR_B_INO, "pci_b");
344 if (ino_bitmap & __BIT(SCZ_UE_INO))
345 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ue, sc, SCZ_UE_INO,
346 "ue");
347 if (ino_bitmap & __BIT(SCZ_CE_INO))
348 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_ce, sc, SCZ_CE_INO,
349 "ce");
350 if (ino_bitmap & __BIT(SCZ_SERR_INO))
351 schizo_set_intr(sc, pbm, PIL_HIGH, schizo_safari_error, sc,
352 SCZ_SERR_INO, "safari");
353
354 if (sc->sc_tomatillo) {
355 /*
356 * Enable the IOCACHE.
357 */
358 uint64_t iocache_csr;
359
360 iocache_csr = TOM_IOCACHE_CSR_WRT_PEN |
361 (1 << TOM_IOCACHE_CSR_POFFSET_SHIFT) |
362 TOM_IOCACHE_CSR_PEN_RDM |
363 TOM_IOCACHE_CSR_PEN_ONE |
364 TOM_IOCACHE_CSR_PEN_LINE;
365 schizo_pbm_write(pbm, SCZ_PCI_IOCACHE_CSR, iocache_csr);
366 }
367
368 config_found(sc->sc_dev, &pba, schizo_print,
369 CFARGS(.devhandle = device_handle(self)));
370 }
371
372 int
schizo_ue(void * vsc)373 schizo_ue(void *vsc)
374 {
375 struct schizo_softc *sc = vsc;
376
377 panic("%s: uncorrectable error", device_xname(sc->sc_dev));
378 return (1);
379 }
380
381 int
schizo_ce(void * vsc)382 schizo_ce(void *vsc)
383 {
384 struct schizo_softc *sc = vsc;
385
386 panic("%s: correctable error", device_xname(sc->sc_dev));
387 return (1);
388 }
389
390 int
schizo_pci_error(void * vpbm)391 schizo_pci_error(void *vpbm)
392 {
393 struct schizo_pbm *sp = vpbm;
394 struct schizo_softc *sc = sp->sp_sc;
395 u_int64_t afsr, afar, ctrl, tfar;
396 u_int32_t csr;
397 char bits[128];
398
399 afsr = schizo_pbm_read(sp, SCZ_PCI_AFSR);
400 afar = schizo_pbm_read(sp, SCZ_PCI_AFAR);
401 ctrl = schizo_pbm_read(sp, SCZ_PCI_CTRL);
402 csr = schizo_cfg_read(sp, PCI_COMMAND_STATUS_REG);
403
404 printf("%s: pci bus %c error\n", device_xname(sc->sc_dev),
405 sp->sp_bus_a ? 'A' : 'B');
406
407 snprintb(bits, sizeof(bits), SCZ_PCIAFSR_BITS, afsr);
408 printf("PCIAFSR=%s\n", bits);
409 printf("PCIAFAR=%" PRIx64 "\n", afar);
410 snprintb(bits, sizeof(bits), SCZ_PCICTRL_BITS, ctrl);
411 printf("PCICTRL=%s\n", bits);
412 #ifdef PCI_COMMAND_STATUS_BITS
413 snprintb(bits, sizeof(bits), PCI_COMMAND_STATUS_BITS, csr);
414 printf("PCICSR=%s\n", bits);
415 #endif
416
417 if (ctrl & SCZ_PCICTRL_MMU_ERR) {
418 ctrl = schizo_pbm_read(sp, SCZ_PCI_IOMMU_CTRL);
419 printf("IOMMUCTRL=%" PRIx64 "\n", ctrl);
420
421 if ((ctrl & TOM_IOMMU_ERR) == 0)
422 goto clear_error;
423
424 if (sc->sc_tomatillo) {
425 tfar = schizo_pbm_read(sp, TOM_PCI_IOMMU_TFAR);
426 printf("IOMMUTFAR=%" PRIx64 "\n", tfar);
427 }
428
429 /* These are non-fatal if target abort was signalled. */
430 if ((ctrl & TOM_IOMMU_ERR_MASK) == TOM_IOMMU_INV_ERR ||
431 ctrl & TOM_IOMMU_ILLTSBTBW_ERR ||
432 ctrl & TOM_IOMMU_BADVA_ERR) {
433 if (csr & PCI_STATUS_TARGET_TARGET_ABORT) {
434 schizo_pbm_write(sp, SCZ_PCI_IOMMU_CTRL, ctrl);
435 goto clear_error;
436 }
437 }
438 }
439
440 panic("%s: %s: fatal", __func__, device_xname(sc->sc_dev));
441
442 clear_error:
443 schizo_cfg_write(sp, PCI_COMMAND_STATUS_REG, csr);
444 schizo_pbm_write(sp, SCZ_PCI_CTRL, ctrl);
445 schizo_pbm_write(sp, SCZ_PCI_AFSR, afsr);
446 return (1);
447 }
448
449 int
schizo_safari_error(void * vsc)450 schizo_safari_error(void *vsc)
451 {
452 struct schizo_softc *sc = vsc;
453
454 printf("%s: safari error\n", device_xname(sc->sc_dev));
455
456 printf("ERRLOG=%" PRIx64 "\n", schizo_read(sc, SCZ_SAFARI_ERRLOG));
457 printf("UE_AFSR=%" PRIx64 "\n", schizo_read(sc, SCZ_UE_AFSR));
458 printf("UE_AFAR=%" PRIx64 "\n", schizo_read(sc, SCZ_UE_AFAR));
459 printf("CE_AFSR=%" PRIx64 "\n", schizo_read(sc, SCZ_CE_AFSR));
460 printf("CE_AFAR=%" PRIx64 "\n", schizo_read(sc, SCZ_CE_AFAR));
461
462 panic("%s: %s: fatal", __func__, device_xname(sc->sc_dev));
463 return (1);
464 }
465
466 void
schizo_init_iommu(struct schizo_softc * sc,struct schizo_pbm * pbm)467 schizo_init_iommu(struct schizo_softc *sc, struct schizo_pbm *pbm)
468 {
469 struct iommu_state *is = &pbm->sp_is;
470 int *vdma = NULL, nitem, tsbsize = 7;
471 u_int32_t iobase = -1;
472 char *name;
473
474 /* punch in our copies */
475 is->is_bustag = pbm->sp_regt;
476 bus_space_subregion(is->is_bustag, pbm->sp_regh,
477 offsetof(struct schizo_pbm_regs, iommu),
478 sizeof(struct iommureg2),
479 &is->is_iommu);
480
481 /*
482 * Separate the men from the boys. If the `virtual-dma'
483 * property exists, use it.
484 */
485 if (!prom_getprop(sc->sc_node, "virtual-dma", sizeof(vdma), &nitem,
486 (void **)&vdma)) {
487 /* Damn. Gotta use these values. */
488 iobase = vdma[0];
489 #define TSBCASE(x) case 1 << ((x) + 23): tsbsize = (x); break
490 switch (vdma[1]) {
491 TSBCASE(1);
492 TSBCASE(2);
493 TSBCASE(3);
494 TSBCASE(4);
495 TSBCASE(5);
496 TSBCASE(6);
497 TSBCASE(7);
498 default:
499 printf("bogus tsb size %x, using 7\n", vdma[1]);
500 tsbsize = 7;
501 }
502 #undef TSBCASE
503 DPRINTF(SDB_BUSMAP, ("schizo_init_iommu: iobase=0x%x\n", iobase));
504 free(vdma, M_DEVBUF);
505 } else {
506 DPRINTF(SDB_BUSMAP, ("schizo_init_iommu: getprop failed, "
507 "using iobase=0x%x, tsbsize=%d\n", iobase, tsbsize));
508 }
509
510 /* give us a nice name.. */
511 name = (char *)kmem_alloc(32, KM_SLEEP);
512 snprintf(name, 32, "%s dvma", device_xname(sc->sc_dev));
513
514 iommu_init(name, is, tsbsize, iobase);
515 }
516
517 int
schizo_print(void * aux,const char * p)518 schizo_print(void *aux, const char *p)
519 {
520
521 if (p == NULL)
522 return (UNCONF);
523 return (QUIET);
524 }
525
526 pcireg_t
schizo_conf_read(pci_chipset_tag_t pc,pcitag_t tag,int reg)527 schizo_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
528 {
529 struct schizo_pbm *sp = pc->cookie;
530 pcireg_t val = (pcireg_t)~0;
531 int s;
532
533 DPRINTF(SDB_CONF, ("%s: tag %lx reg %x ", __func__, (long)tag, reg));
534 if (PCITAG_NODE(tag) != -1 && (unsigned int)reg < PCI_CONF_SIZE) {
535 s = splhigh();
536 struct cpu_info *ci = curcpu();
537 ci->ci_pci_probe = true;
538 membar_Sync();
539 val = bus_space_read_4(sp->sp_cfgt, sp->sp_cfgh,
540 PCITAG_OFFSET(tag) + reg);
541 membar_Sync();
542 if (ci->ci_pci_fault)
543 val = (pcireg_t)~0;
544 ci->ci_pci_probe = ci->ci_pci_fault = false;
545 splx(s);
546 }
547 DPRINTF(SDB_CONF, (" returning %08x\n", (u_int)val));
548 return (val);
549 }
550
551 void
schizo_conf_write(pci_chipset_tag_t pc,pcitag_t tag,int reg,pcireg_t data)552 schizo_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
553 {
554 struct schizo_pbm *sp = pc->cookie;
555
556 DPRINTF(SDB_CONF, ("%s: tag %lx; reg %x; data %x", __func__,
557 (long)tag, reg, (int)data));
558
559 /* If we don't know it, just punt it. */
560 if (PCITAG_NODE(tag) == -1) {
561 DPRINTF(SDB_CONF, (" .. bad addr\n"));
562 return;
563 }
564
565 if ((unsigned int)reg >= PCI_CONF_SIZE)
566 return;
567
568 bus_space_write_4(sp->sp_cfgt, sp->sp_cfgh,
569 PCITAG_OFFSET(tag) + reg, data);
570 DPRINTF(SDB_CONF, (" .. done\n"));
571 }
572
573 void
schizo_set_intr(struct schizo_softc * sc,struct schizo_pbm * pbm,int ipl,int (* handler)(void *),void * arg,int ino,const char * what)574 schizo_set_intr(struct schizo_softc *sc, struct schizo_pbm *pbm, int ipl,
575 int (*handler)(void *), void *arg, int ino, const char *what)
576 {
577 struct intrhand *ih;
578 u_int64_t mapoff, clroff;
579 uintptr_t intrregs;
580
581 DPRINTF(SDB_INTR, ("%s: ino %x ign %x fn %p arg %p", __func__,
582 ino, sc->sc_ign, handler, arg));
583
584 mapoff = offsetof(struct schizo_pbm_regs, imap[ino]);
585 clroff = offsetof(struct schizo_pbm_regs, iclr[ino]);
586 ino |= sc->sc_ign;
587
588 DPRINTF(SDB_INTR, (" mapoff %" PRIx64 " clroff %" PRIx64 "\n",
589 mapoff, clroff));
590
591 ih = intrhand_alloc();
592
593 ih->ih_arg = arg;
594 intrregs = (uintptr_t)bus_space_vaddr(pbm->sp_regt, pbm->sp_intrh);
595 ih->ih_map = (uint64_t *)(uintptr_t)(intrregs + mapoff);
596 ih->ih_clr = (uint64_t *)(uintptr_t)(intrregs + clroff);
597 ih->ih_fun = handler;
598 ih->ih_pil = ipl;
599 ih->ih_number = INTVEC(schizo_pbm_read(pbm, mapoff));
600 ih->ih_pending = 0;
601
602 intr_establish(ipl, ipl != IPL_VM, ih);
603
604 schizo_pbm_write(pbm, mapoff,
605 ih->ih_number | INTMAP_V | (CPU_UPAID << INTMAP_TID_SHIFT));
606 schizo_pbm_write(pbm, clroff, 0);
607 }
608
609 bus_space_tag_t
schizo_alloc_mem_tag(struct schizo_pbm * sp)610 schizo_alloc_mem_tag(struct schizo_pbm *sp)
611 {
612 return (schizo_alloc_bus_tag(sp, "mem", PCI_MEMORY_BUS_SPACE));
613 }
614
615 bus_space_tag_t
schizo_alloc_io_tag(struct schizo_pbm * sp)616 schizo_alloc_io_tag(struct schizo_pbm *sp)
617 {
618 return (schizo_alloc_bus_tag(sp, "io", PCI_IO_BUS_SPACE));
619 }
620
621 bus_space_tag_t
schizo_alloc_config_tag(struct schizo_pbm * sp)622 schizo_alloc_config_tag(struct schizo_pbm *sp)
623 {
624 return (schizo_alloc_bus_tag(sp, "cfg", PCI_CONFIG_BUS_SPACE));
625 }
626
627 bus_space_tag_t
schizo_alloc_bus_tag(struct schizo_pbm * pbm,const char * name,int type)628 schizo_alloc_bus_tag(struct schizo_pbm *pbm, const char *name, int type)
629 {
630 struct schizo_softc *sc = pbm->sp_sc;
631 bus_space_tag_t bt;
632
633 bt = kmem_zalloc(sizeof(*bt), KM_SLEEP);
634 bt->cookie = pbm;
635 bt->parent = sc->sc_bustag;
636 bt->type = type;
637 bt->sparc_bus_map = schizo_bus_map;
638 bt->sparc_bus_mmap = schizo_bus_mmap;
639 bt->sparc_intr_establish = schizo_intr_establish;
640 return (bt);
641 }
642
643 bus_dma_tag_t
schizo_alloc_dma_tag(struct schizo_pbm * pbm)644 schizo_alloc_dma_tag(struct schizo_pbm *pbm)
645 {
646 struct schizo_softc *sc = pbm->sp_sc;
647 bus_dma_tag_t dt, pdt = sc->sc_dmat;
648
649 dt = kmem_zalloc(sizeof(*dt), KM_SLEEP);
650 dt->_cookie = pbm;
651 dt->_parent = pdt;
652 #define PCOPY(x) dt->x = pdt->x
653 dt->_dmamap_create = schizo_dmamap_create;
654 PCOPY(_dmamap_destroy);
655 dt->_dmamap_load = iommu_dvmamap_load;
656 PCOPY(_dmamap_load_mbuf);
657 PCOPY(_dmamap_load_uio);
658 dt->_dmamap_load_raw = iommu_dvmamap_load_raw;
659 dt->_dmamap_unload = iommu_dvmamap_unload;
660 dt->_dmamap_sync = iommu_dvmamap_sync;
661 dt->_dmamem_alloc = iommu_dvmamem_alloc;
662 dt->_dmamem_free = iommu_dvmamem_free;
663 dt->_dmamem_map = iommu_dvmamem_map;
664 dt->_dmamem_unmap = iommu_dvmamem_unmap;
665 PCOPY(_dmamem_mmap);
666 #undef PCOPY
667 return (dt);
668 }
669
670 pci_chipset_tag_t
schizo_alloc_chipset(struct schizo_pbm * pbm,int node,pci_chipset_tag_t pc)671 schizo_alloc_chipset(struct schizo_pbm *pbm, int node, pci_chipset_tag_t pc)
672 {
673 pci_chipset_tag_t npc;
674
675 npc = kmem_alloc(sizeof *npc, KM_SLEEP);
676 memcpy(npc, pc, sizeof *pc);
677 npc->cookie = pbm;
678 npc->rootnode = node;
679 npc->spc_conf_read = schizo_conf_read;
680 npc->spc_conf_write = schizo_conf_write;
681 npc->spc_intr_map = schizo_pci_intr_map;
682 npc->spc_intr_establish = schizo_pci_intr_establish;
683 npc->spc_find_ino = NULL;
684 return (npc);
685 }
686
687 int
schizo_dmamap_create(bus_dma_tag_t t,bus_size_t size,int nsegments,bus_size_t maxsegsz,bus_size_t boundary,int flags,bus_dmamap_t * dmamp)688 schizo_dmamap_create(bus_dma_tag_t t, bus_size_t size,
689 int nsegments, bus_size_t maxsegsz, bus_size_t boundary, int flags,
690 bus_dmamap_t *dmamp)
691 {
692 struct schizo_pbm *pbm = t->_cookie;
693 int error;
694
695 error = bus_dmamap_create(t->_parent, size, nsegments, maxsegsz,
696 boundary, flags, dmamp);
697 if (error == 0)
698 (*dmamp)->_dm_cookie = &pbm->sp_sb;
699 return error;
700 }
701
702 static struct schizo_range *
get_schizorange(struct schizo_pbm * pbm,int ss)703 get_schizorange(struct schizo_pbm *pbm, int ss)
704 {
705 int i;
706
707 for (i = 0; i < pbm->sp_nrange; i++) {
708 if (((pbm->sp_range[i].cspace >> 24) & 0x03) == ss)
709 return (&pbm->sp_range[i]);
710 }
711 /* not found */
712 return (NULL);
713 }
714
715 int
schizo_bus_map(bus_space_tag_t t,bus_addr_t offset,bus_size_t size,int flags,vaddr_t unused,bus_space_handle_t * hp)716 schizo_bus_map(bus_space_tag_t t, bus_addr_t offset, bus_size_t size,
717 int flags, vaddr_t unused, bus_space_handle_t *hp)
718 {
719 bus_addr_t paddr;
720 struct schizo_pbm *pbm = t->cookie;
721 struct schizo_softc *sc = pbm->sp_sc;
722 struct schizo_range *sr;
723 int ss;
724
725 DPRINTF(SDB_BUSMAP, ("schizo_bus_map: type %d off %qx sz %qx flags %d",
726 t->type,
727 (unsigned long long)offset,
728 (unsigned long long)size,
729 flags));
730
731 /*
732 * BUS_SPACE_MAP_PREFETCHABLE causes hard hangs on schizo, so weed it
733 * out for now
734 */
735 flags &= ~BUS_SPACE_MAP_PREFETCHABLE;
736
737 ss = sparc_pci_childspace(t->type);
738 DPRINTF(SDB_BUSMAP, (" cspace %d\n", ss));
739
740 sr = get_schizorange(pbm, ss);
741 if (sr != NULL) {
742 paddr = BUS_ADDR(sr->phys_hi, sr->phys_lo + offset);
743 DPRINTF(SDB_BUSMAP, ("%s: mapping paddr "
744 "space %lx offset %lx paddr %qx\n",
745 __func__, (long)ss, (long)offset,
746 (unsigned long long)paddr));
747 return ((*sc->sc_bustag->sparc_bus_map)(t, paddr, size,
748 flags, 0, hp));
749 }
750 DPRINTF(SDB_BUSMAP, ("%s: FAILED\n", __func__));
751 return (EINVAL);
752 }
753
754 static paddr_t
schizo_bus_mmap(bus_space_tag_t t,bus_addr_t paddr,off_t off,int prot,int flags)755 schizo_bus_mmap(bus_space_tag_t t, bus_addr_t paddr, off_t off, int prot,
756 int flags)
757 {
758 bus_addr_t offset = paddr;
759 struct schizo_pbm *pbm = t->cookie;
760 struct schizo_softc *sc = pbm->sp_sc;
761 struct schizo_range *sr;
762 int ss;
763
764 /*
765 * BUS_SPACE_MAP_PREFETCHABLE causes hard hangs on schizo, so weed it
766 * out for now
767 */
768 flags &= ~BUS_SPACE_MAP_PREFETCHABLE;
769
770 ss = sparc_pci_childspace(t->type);
771
772 DPRINTF(SDB_BUSMAP, ("schizo_bus_mmap: prot %d flags %d pa %qx\n",
773 prot, flags, (unsigned long long)paddr));
774
775 sr = get_schizorange(pbm, ss);
776 if (sr != NULL) {
777 paddr = BUS_ADDR(sr->phys_hi, sr->phys_lo + offset);
778 DPRINTF(SDB_BUSMAP, ("%s: mapping paddr "
779 "space %lx offset %lx paddr %qx\n",
780 __func__, (long)ss, (long)offset,
781 (unsigned long long)paddr));
782 return (bus_space_mmap(sc->sc_bustag, paddr, off,
783 prot, flags));
784 }
785 DPRINTF(SDB_BUSMAP, ("%s: FAILED\n", __func__));
786 return (-1);
787 }
788
789 /*
790 * Set the IGN for this schizo into the handle.
791 */
792 int
schizo_pci_intr_map(const struct pci_attach_args * pa,pci_intr_handle_t * ihp)793 schizo_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
794 {
795 struct schizo_pbm *pbm = pa->pa_pc->cookie;
796 struct schizo_softc *sc = pbm->sp_sc;
797
798 DPRINTF(SDB_INTMAP, ("IGN %x", *ihp));
799 *ihp |= sc->sc_ign;
800 DPRINTF(SDB_INTMAP, (" adjusted to %x\n", *ihp));
801 return (0);
802 }
803
804 static void *
schizo_intr_establish(bus_space_tag_t t,int ihandle,int level,int (* handler)(void *),void * arg,void (* fastvec)(void))805 schizo_intr_establish(bus_space_tag_t t, int ihandle, int level,
806 int (*handler)(void *), void *arg, void (*fastvec)(void) /* ignored */)
807 {
808 struct schizo_pbm *pbm = t->cookie;
809 struct intrhand *ih = NULL;
810 uint64_t mapoff, clroff;
811 uintptr_t intrregs;
812 volatile uint64_t *intrmapptr = NULL, *intrclrptr = NULL;
813 int ino;
814 long vec;
815
816 vec = INTVEC(ihandle);
817 ino = INTINO(vec);
818
819 ih = intrhand_alloc();
820
821 DPRINTF(SDB_INTR, ("\n%s: ihandle %x level %d fn %p arg %p\n", __func__,
822 ihandle, level, handler, arg));
823
824 if (level == IPL_NONE)
825 level = INTLEV(vec);
826 if (level == IPL_NONE) {
827 printf(": no IPL, setting IPL 2.\n");
828 level = 2;
829 }
830
831 mapoff = offsetof(struct schizo_pbm_regs, imap[ino]);
832 clroff = offsetof(struct schizo_pbm_regs, iclr[ino]);
833
834 DPRINTF(SDB_INTR, ("%s: intr %x: %p mapoff %" PRIx64 " clroff %"
835 PRIx64 "\n", __func__, ino, intrlev[ino], mapoff, clroff));
836
837 ih->ih_ivec = ihandle;
838
839 intrregs = (uintptr_t)bus_space_vaddr(pbm->sp_regt, pbm->sp_intrh);
840 intrmapptr = (uint64_t *)(uintptr_t)(intrregs + mapoff);
841 intrclrptr = (uint64_t *)(uintptr_t)(intrregs + clroff);
842
843 if (INTIGN(vec) == 0)
844 ino |= schizo_pbm_readintr(pbm, mapoff) & INTMAP_IGN;
845 else
846 ino |= vec & INTMAP_IGN;
847
848 /* Register the map and clear intr registers */
849 ih->ih_map = intrmapptr;
850 ih->ih_clr = intrclrptr;
851
852 ih->ih_fun = handler;
853 ih->ih_arg = arg;
854 ih->ih_pil = level;
855 ih->ih_number = ino;
856 ih->ih_pending = 0;
857
858 DPRINTF(SDB_INTR, (
859 "; installing handler %p arg %p with inr %x pil %u\n",
860 handler, arg, ino, (u_int)ih->ih_pil));
861
862 intr_establish(ih->ih_pil, level != IPL_VM, ih);
863
864 /*
865 * Enable the interrupt now we have the handler installed.
866 * Read the current value as we can't change it besides the
867 * valid bit so so make sure only this bit is changed.
868 */
869 if (intrmapptr) {
870 u_int64_t imap;
871
872 imap = schizo_pbm_readintr(pbm, mapoff);
873 DPRINTF(SDB_INTR, ("; read intrmap = %016qx",
874 (unsigned long long)imap));
875 imap |= INTMAP_V;
876 imap |= (CPU_UPAID << INTMAP_TID_SHIFT);
877 DPRINTF(SDB_INTR, ("; addr of intrmapptr = %p", intrmapptr));
878 DPRINTF(SDB_INTR, ("; writing intrmap = %016qx\n",
879 (unsigned long long)imap));
880 schizo_pbm_writeintr(pbm, mapoff, imap);
881 imap = schizo_pbm_readintr(pbm, mapoff);
882 DPRINTF(SDB_INTR, ("; reread intrmap = %016qx",
883 (unsigned long long)imap));
884 ih->ih_number |= imap & INTMAP_INR;
885 }
886 if (intrclrptr) {
887 /* set state to IDLE */
888 schizo_pbm_writeintr(pbm, clroff, 0);
889 }
890
891 return (ih);
892 }
893
894 static void *
schizo_pci_intr_establish(pci_chipset_tag_t pc,pci_intr_handle_t ih,int level,int (* func)(void *),void * arg)895 schizo_pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level,
896 int (*func)(void *), void *arg)
897 {
898 void *cookie;
899 struct schizo_pbm *pbm = (struct schizo_pbm *)pc->cookie;
900
901 DPRINTF(SDB_INTR, ("%s: ih %lx; level %d", __func__, (u_long)ih, level));
902 cookie = bus_intr_establish(pbm->sp_memt, ih, level, func, arg);
903
904 DPRINTF(SDB_INTR, ("; returning handle %p\n", cookie));
905 return (cookie);
906 }
907
908 #ifdef DEBUG
909 void
schizo_print_regs(int unit,int what)910 schizo_print_regs(int unit, int what)
911 {
912 device_t dev;
913 struct schizo_softc *sc;
914 struct schizo_pbm *pbm;
915 const struct schizo_regname *r;
916 int i;
917 u_int64_t reg;
918
919 dev = device_find_by_driver_unit("schizo", unit);
920 if (dev == NULL) {
921 printf("Can't find device schizo%d\n", unit);
922 return;
923 }
924
925 if (!what) {
926 printf("0x01: Safari registers\n");
927 printf("0x02: PCI registers\n");
928 printf("0x04: Scratch pad registers (Tomatillo only)\n");
929 printf("0x08: IOMMU registers\n");
930 printf("0x10: Streaming cache registers (Schizo only)\n");
931 printf("0x20: Interrupt registers\n");
932 printf("0x40: I-chip registers (Tomatillo only)\n");
933 return;
934 }
935 sc = device_private(dev);
936 pbm = sc->sc_pbm;
937 printf("%s (leaf %c) registers:\n", device_xname(sc->sc_dev),
938 pbm->sp_bus_a ? 'A' : 'B');
939
940 printf(" Safari registers:\n");
941 if (what & 0x01) {
942 for (r = schizo_regnames; r->size != 0; ++r)
943 for (i = 0; i <= r->n_reg; i += r->size) {
944 if ((!sc->sc_tomatillo &&
945 !(r->type & REG_TYPE_SCHIZO)) ||
946 (sc->sc_tomatillo &&
947 !(r->type & REG_TYPE_TOMATILLO)))
948 continue;
949 switch (r->size) {
950 case 1:
951 reg = schizo_read_1(sc, r->offset + i);
952 break;
953 case 8:
954 /* fallthrough */
955 default:
956 reg = schizo_read(sc, r->offset + i);
957 break;
958 }
959 printf("0x%06" PRIx64 " = 0x%016" PRIx64 " (%s",
960 r->offset + i, reg, r->name);
961 if (r->n_reg)
962 printf(" %d)\n", i / r->size);
963 else
964 printf(")\n");
965 }
966 }
967
968 if (what & 0x02) {
969 printf(" PCI registers:\n");
970 for (r = schizo_pbm_regnames; r->size != 0; ++r)
971 for (i = 0; i <= r->n_reg; i += r->size) {
972 if ((!sc->sc_tomatillo &&
973 !(r->type & REG_TYPE_SCHIZO)) ||
974 (sc->sc_tomatillo &&
975 !(r->type & REG_TYPE_TOMATILLO)))
976 continue;
977 if ((pbm->sp_bus_a &&
978 !(r->type & REG_TYPE_LEAF_A)) ||
979 (!pbm->sp_bus_a &&
980 !(r->type & REG_TYPE_LEAF_B)))
981 continue;
982 reg = schizo_pbm_read(pbm, r->offset + i);
983 printf("0x%06" PRIx64 " = 0x%016" PRIx64 ""
984 " (%s", r->offset + i, reg, r->name);
985 if (r->n_reg)
986 printf(" %d)\n", i / r->size);
987 else
988 printf(")\n");
989 }
990 }
991
992 if (what & 0x04 && sc->sc_tomatillo) {
993 printf(" Scratch pad registers:\n");
994 for (r = tomatillo_scratch_regnames; r->size != 0; ++r)
995 for (i = 0; i <= r->n_reg; i += r->size) {
996 reg = schizo_pbm_read(pbm, r->offset + i);
997 printf("0x%06" PRIx64 " = 0x%016" PRIx64 ""
998 " (%s", r->offset + i, reg, r->name);
999 if (r->n_reg)
1000 printf(" %d)\n", i / r->size);
1001 else
1002 printf(")\n");
1003 }
1004 }
1005
1006 if (what & 0x08) {
1007 printf(" IOMMU registers:\n");
1008 for (r = schizo_iommu_regnames; r->size != 0; ++r)
1009 for (i = 0; i <= r->n_reg; i += r->size) {
1010 if ((!sc->sc_tomatillo &&
1011 !(r->type & REG_TYPE_SCHIZO)) ||
1012 (sc->sc_tomatillo &&
1013 !(r->type & REG_TYPE_TOMATILLO)))
1014 continue;
1015 reg = schizo_pbm_read(pbm, r->offset + i);
1016 printf("0x%06" PRIx64 " = 0x%016" PRIx64 ""
1017 " (%s", r->offset + i, reg, r->name);
1018 if (r->n_reg)
1019 printf(" %d)\n", i / r->size);
1020 else
1021 printf(")\n");
1022 }
1023 }
1024
1025 if (what & 0x10 && !sc->sc_tomatillo) {
1026 printf(" Streaming cache registers:\n");
1027 for (r = schizo_stream_regnames; r->size != 0; ++r)
1028 for (i = 0; i <= r->n_reg; i += r->size) {
1029 reg = schizo_pbm_read(pbm, r->offset + i);
1030 printf("0x%06" PRIx64 " = 0x%016" PRIx64 ""
1031 " (%s", r->offset + i, reg, r->name);
1032 if (r->n_reg)
1033 printf(" %d)\n", i / r->size);
1034 else
1035 printf(")\n");
1036 }
1037 }
1038
1039 if (what & 0x20) {
1040 printf(" Interrupt registers:\n");
1041 for (r = schizo_intr_regnames; r->size != 0; ++r)
1042 for (i = 0; i <= r->n_reg; i += r->size) {
1043 if ((!sc->sc_tomatillo &&
1044 !(r->type & REG_TYPE_SCHIZO)) ||
1045 (sc->sc_tomatillo &&
1046 !(r->type & REG_TYPE_TOMATILLO)))
1047 continue;
1048 reg = schizo_pbm_readintr(pbm, r->offset + i);
1049 printf("0x%06" PRIx64 " = 0x%016" PRIx64 ""
1050 " (%s", r->offset + i, reg, r->name);
1051 if (r->n_reg)
1052 printf(" %d)\n", i / r->size);
1053 else
1054 printf(")\n");
1055 }
1056 }
1057
1058 if (what & 0x40 && sc->sc_tomatillo) {
1059 printf(" I-chip registers:\n");
1060 for (r = tomatillo_ichip_regnames; r->size != 0; ++r)
1061 for (i = 0; i <= r->n_reg; i += r->size) {
1062 if ((sc->sc_tomatillo &&
1063 !(r->type & REG_TYPE_TOMATILLO)))
1064 continue;
1065 reg = tomatillo_pbm_readichip(pbm,
1066 r->offset + i);
1067 printf("0x%06" PRIx64 " = 0x%016" PRIx64 ""
1068 " (%s", r->offset + i, reg, r->name);
1069 if (r->n_reg)
1070 printf(" %d)\n", i / r->size);
1071 else
1072 printf(")\n");
1073 }
1074 }
1075 }
1076 #endif
1077