1 /* $NetBSD: s3c2410_intr.c,v 1.14 2022/09/27 06:36:43 skrll Exp $ */
2
3 /*
4 * Copyright (c) 2003 Genetec corporation. All rights reserved.
5 * Written by Hiroyuki Bessho for Genetec corporation.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of Genetec corporation may not be used to endorse
16 * or promote products derived from this software without specific prior
17 * written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP.
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /*
33 * IRQ handler for Samsung S3C2410 processor.
34 * It has integrated interrupt controller.
35 */
36
37 #include <sys/cdefs.h>
38 __KERNEL_RCSID(0, "$NetBSD: s3c2410_intr.c,v 1.14 2022/09/27 06:36:43 skrll Exp $");
39
40 #include <sys/param.h>
41 #include <sys/systm.h>
42
43 #include <sys/bus.h>
44 #include <machine/intr.h>
45
46 #include <arm/cpufunc.h>
47
48 #include <arm/s3c2xx0/s3c2410reg.h>
49 #include <arm/s3c2xx0/s3c2410var.h>
50
51 /*
52 * interrupt dispatch table.
53 */
54
55 struct s3c2xx0_intr_dispatch handler[ICU_LEN];
56
57
58 volatile int intr_mask;
59 #ifdef __HAVE_FAST_SOFTINTS
60 volatile int softint_pending;
61 volatile int soft_intr_mask;
62 #endif
63 volatile int global_intr_mask = 0; /* mask some interrupts at all spl level */
64
65 /* interrupt masks for each level */
66 int s3c2xx0_imask[NIPL];
67 int s3c2xx0_ilevel[ICU_LEN];
68 #ifdef __HAVE_FAST_SOFTINTS
69 int s3c24x0_soft_imask[NIPL];
70 #endif
71
72 vaddr_t intctl_base; /* interrupt controller registers */
73 #define icreg(offset) \
74 (*(volatile uint32_t *)(intctl_base+(offset)))
75
76 #ifdef __HAVE_FAST_SOFTINTS
77 /*
78 * Map a software interrupt queue to an interrupt priority level.
79 */
80 static const int si_to_ipl[] = {
81 [SI_SOFTBIO] = IPL_SOFTBIO,
82 [SI_SOFTCLOCK] = IPL_SOFTCLOCK,
83 [SI_SOFTNET] = IPL_SOFTNET,
84 [SI_SOFTSERIAL] = IPL_SOFTSERIAL,
85 };
86 #endif
87
88 #define PENDING_CLEAR_MASK (~0)
89
90 /*
91 * called from irq_entry.
92 */
93 void s3c2410_irq_handler(struct clockframe *);
94 void
s3c2410_irq_handler(struct clockframe * frame)95 s3c2410_irq_handler(struct clockframe *frame)
96 {
97 uint32_t irqbits;
98 int irqno;
99 int saved_spl_level;
100
101 saved_spl_level = curcpl();
102
103 #ifdef DIAGNOSTIC
104 if (curcpu()->ci_intr_depth > 10)
105 panic("nested intr too deep");
106 #endif
107
108 while ((irqbits = icreg(INTCTL_INTPND)) != 0) {
109
110 /* Note: Only one bit in INTPND register is set */
111
112 irqno = icreg(INTCTL_INTOFFSET);
113
114 #ifdef DIAGNOSTIC
115 if (__predict_false((irqbits & (1<<irqno)) == 0)) {
116 /* This shouldn't happen */
117 printf("INTOFFSET=%d, INTPND=%x\n", irqno, irqbits);
118 break;
119 }
120 #endif
121 /* raise spl to stop interrupts of lower priorities */
122 if (saved_spl_level < handler[irqno].level)
123 s3c2xx0_setipl(handler[irqno].level);
124
125 /* clear pending bit */
126 icreg(INTCTL_SRCPND) = PENDING_CLEAR_MASK & (1 << irqno);
127 icreg(INTCTL_INTPND) = PENDING_CLEAR_MASK & (1 << irqno);
128
129 enable_interrupts(I32_bit); /* allow nested interrupts */
130
131 (*handler[irqno].func) (
132 handler[irqno].cookie == 0
133 ? frame : handler[irqno].cookie);
134
135 disable_interrupts(I32_bit);
136
137 /* restore spl to that was when this interrupt happen */
138 s3c2xx0_setipl(saved_spl_level);
139
140 }
141
142 #ifdef __HAVE_FAST_SOFTINTS
143 cpu_dosoftints();
144 #endif
145 }
146
147 /*
148 * Handler for main IRQ of cascaded interrupts.
149 */
150 static int
cascade_irq_handler(void * cookie)151 cascade_irq_handler(void *cookie)
152 {
153 int index = (int)cookie - 1;
154 uint32_t irqbits;
155 int irqno, i;
156 int save = disable_interrupts(I32_bit);
157
158 KASSERT(0 <= index && index <= 3);
159
160 irqbits = icreg(INTCTL_SUBSRCPND) &
161 ~icreg(INTCTL_INTSUBMSK) & (0x07 << (3*index));
162
163 for (irqno = 3*index; irqbits; ++irqno) {
164 if ((irqbits & (1<<irqno)) == 0)
165 continue;
166
167 /* clear pending bit */
168 irqbits &= ~(1<<irqno);
169 icreg(INTCTL_SUBSRCPND) = (1 << irqno);
170
171 /* allow nested interrupts. SPL is already set
172 * correctly by main handler. */
173 restore_interrupts(save);
174
175 i = S3C2410_SUBIRQ_MIN + irqno;
176 (* handler[i].func)(handler[i].cookie);
177
178 disable_interrupts(I32_bit);
179 }
180
181 return 1;
182 }
183
184
185 static const uint8_t subirq_to_main[] = {
186 S3C2410_INT_UART0,
187 S3C2410_INT_UART0,
188 S3C2410_INT_UART0,
189 S3C2410_INT_UART1,
190 S3C2410_INT_UART1,
191 S3C2410_INT_UART1,
192 S3C2410_INT_UART2,
193 S3C2410_INT_UART2,
194 S3C2410_INT_UART2,
195 S3C24X0_INT_ADCTC,
196 S3C24X0_INT_ADCTC,
197 };
198
199 void *
s3c24x0_intr_establish(int irqno,int level,int type,int (* func)(void *),void * cookie)200 s3c24x0_intr_establish(int irqno, int level, int type,
201 int (* func) (void *), void *cookie)
202 {
203 int save;
204
205 if (irqno < 0 || irqno >= ICU_LEN ||
206 type < IST_NONE || IST_EDGE_BOTH < type)
207 panic("intr_establish: bogus irq or type");
208
209 save = disable_interrupts(I32_bit);
210
211 handler[irqno].cookie = cookie;
212 handler[irqno].func = func;
213 handler[irqno].level = level;
214
215 if (irqno >= S3C2410_SUBIRQ_MIN) {
216 /* cascaded interrupts. */
217 int main_irqno;
218 int i = (irqno - S3C2410_SUBIRQ_MIN);
219
220 main_irqno = subirq_to_main[i];
221
222 /* establish main irq if first time
223 * be careful that cookie shouldn't be 0 */
224 if (handler[main_irqno].func != cascade_irq_handler)
225 s3c24x0_intr_establish(main_irqno, level, type,
226 cascade_irq_handler, (void *)((i/3) + 1));
227
228 /* unmask it in submask register */
229 icreg(INTCTL_INTSUBMSK) &= ~(1<<i);
230
231 restore_interrupts(save);
232 return &handler[irqno];
233 }
234
235 s3c2xx0_update_intr_masks(irqno, level);
236
237 /*
238 * set trigger type for external interrupts 0..3
239 */
240 if (irqno <= S3C24X0_INT_EXT(3)) {
241 /*
242 * Update external interrupt control
243 */
244 s3c2410_setup_extint(irqno, type);
245 }
246
247 s3c2xx0_setipl(curcpl());
248
249 restore_interrupts(save);
250
251 return &handler[irqno];
252 }
253
254
255 static void
init_interrupt_masks(void)256 init_interrupt_masks(void)
257 {
258 int i;
259
260 for (i=0; i < NIPL; ++i)
261 s3c2xx0_imask[i] = 0;
262
263 #ifdef __HAVE_FAST_SOFTINTS
264 s3c24x0_soft_imask[IPL_NONE] = SI_TO_IRQBIT(SI_SOFTSERIAL) |
265 SI_TO_IRQBIT(SI_SOFTNET) | SI_TO_IRQBIT(SI_SOFTCLOCK) |
266 SI_TO_IRQBIT(SI_SOFT);
267
268 s3c24x0_soft_imask[IPL_SOFT] = SI_TO_IRQBIT(SI_SOFTSERIAL) |
269 SI_TO_IRQBIT(SI_SOFTNET) | SI_TO_IRQBIT(SI_SOFTCLOCK);
270
271 /*
272 * splsoftclock() is the only interface that users of the
273 * generic software interrupt facility have to block their
274 * soft intrs, so splsoftclock() must also block IPL_SOFT.
275 */
276 s3c24x0_soft_imask[IPL_SOFTCLOCK] = SI_TO_IRQBIT(SI_SOFTSERIAL) |
277 SI_TO_IRQBIT(SI_SOFTNET);
278
279 /*
280 * splsoftnet() must also block splsoftclock(), since we don't
281 * want timer-driven network events to occur while we're
282 * processing incoming packets.
283 */
284 s3c24x0_soft_imask[IPL_SOFTNET] = SI_TO_IRQBIT(SI_SOFTSERIAL);
285
286 for (i = IPL_BIO; i < IPL_SOFTSERIAL; ++i)
287 s3c24x0_soft_imask[i] = SI_TO_IRQBIT(SI_SOFTSERIAL);
288 #endif
289 }
290
291 void
s3c2410_intr_init(struct s3c24x0_softc * sc)292 s3c2410_intr_init(struct s3c24x0_softc *sc)
293 {
294 intctl_base = (vaddr_t) bus_space_vaddr(sc->sc_sx.sc_iot,
295 sc->sc_sx.sc_intctl_ioh);
296
297 s3c2xx0_intr_mask_reg = (uint32_t *)(intctl_base + INTCTL_INTMSK);
298
299 /* clear all pending interrupt */
300 icreg(INTCTL_SRCPND) = ~0;
301 icreg(INTCTL_INTPND) = ~0;
302
303 /* mask all sub interrupts */
304 icreg(INTCTL_INTSUBMSK) = 0x7ff;
305
306 init_interrupt_masks();
307
308 s3c2xx0_intr_init(handler, ICU_LEN);
309
310 }
311
312
313 /*
314 * mask/unmask sub interrupts
315 */
316 void
s3c2410_mask_subinterrupts(int bits)317 s3c2410_mask_subinterrupts(int bits)
318 {
319 int psw = disable_interrupts(IF32_bits);
320 icreg(INTCTL_INTSUBMSK) |= bits;
321 restore_interrupts(psw);
322 }
323
324 void
s3c2410_unmask_subinterrupts(int bits)325 s3c2410_unmask_subinterrupts(int bits)
326 {
327 int psw = disable_interrupts(IF32_bits);
328 icreg(INTCTL_INTSUBMSK) &= ~bits;
329 restore_interrupts(psw);
330 }
331
332 /*
333 * Update external interrupt control
334 */
335 static const u_char s3c24x0_ist[] = {
336 EXTINTR_LOW, /* NONE */
337 EXTINTR_FALLING, /* PULSE */
338 EXTINTR_FALLING, /* EDGE */
339 EXTINTR_LOW, /* LEVEL */
340 EXTINTR_HIGH,
341 EXTINTR_RISING,
342 EXTINTR_BOTH,
343 };
344
345 void
s3c2410_setup_extint(int extint,int type)346 s3c2410_setup_extint(int extint, int type)
347 {
348 uint32_t reg;
349 u_int trig;
350 int i = extint % 8;
351 int regidx = extint/8; /* GPIO_EXTINT[0:2] */
352 int save;
353
354 trig = s3c24x0_ist[type];
355
356 save = disable_interrupts(I32_bit);
357
358 reg = bus_space_read_4(s3c2xx0_softc->sc_iot,
359 s3c2xx0_softc->sc_gpio_ioh,
360 GPIO_EXTINT(regidx));
361
362 reg = reg & ~(0x07 << (4*i));
363 reg |= trig << (4*i);
364
365 bus_space_write_4(s3c2xx0_softc->sc_iot, s3c2xx0_softc->sc_gpio_ioh,
366 GPIO_EXTINT(regidx), reg);
367
368 restore_interrupts(save);
369 }
370