xref: /netbsd-src/sys/arch/arm/rockchip/rk_eqos.c (revision 90313c06e62e910bf0d1bb24faa9d17dcefd0ab6)
1 /*	$NetBSD: rk_eqos.c,v 1.3 2024/02/07 04:20:27 msaitoh Exp $	*/
2 
3 /*-
4  * Copyright (c) 2022 Ryo Shimizu
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
17  * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
20  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
24  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
25  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26  * POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: rk_eqos.c,v 1.3 2024/02/07 04:20:27 msaitoh Exp $");
31 
32 #include <sys/param.h>
33 #include <sys/bus.h>
34 #include <sys/device.h>
35 #include <sys/rndsource.h>
36 
37 #include <net/if_ether.h>
38 #include <net/if_media.h>
39 
40 #include <dev/fdt/fdtvar.h>
41 #include <dev/fdt/syscon.h>
42 
43 #include <dev/mii/miivar.h>
44 #include <dev/ic/dwc_eqos_var.h>
45 
46 struct rk_eqos_softc {
47 	struct eqos_softc sc_base;
48 
49 	struct syscon *sc_grf;
50 	struct syscon *sc_php_grf;
51 	int sc_id;	/* ethernet0 or 1? */
52 };
53 
54 static int rk_eqos_match(device_t, cfdata_t, void *);
55 static void rk_eqos_attach(device_t, device_t, void *);
56 
57 struct rk_eqos_ops {
58 	void (*set_mode_rgmii)(struct rk_eqos_softc *, int, int);
59 	void (*set_speed_rgmii)(struct rk_eqos_softc *, int);
60 	void (*clock_selection)(struct rk_eqos_softc *, int);
61 	int (*get_unit)(struct rk_eqos_softc *, int);
62 };
63 
64 CFATTACH_DECL_NEW(rk_eqos, sizeof(struct rk_eqos_softc),
65     rk_eqos_match, rk_eqos_attach, NULL, NULL);
66 
67 /*
68  * RK3588 specific
69  */
70 #define RK3588_ETHERNET1_ADDR			0xfe1c0000
71 
72 /* grf */
73 #define RK3588_GRF_GMAC_TXRXCLK_DELAY_EN_REG	(0x0300 + (4 * 7))
74 #define  RK3588_GMAC_RXCLK_DELAY_EN(id)		__BIT(3 + 2 * (id))
75 #define   RK3588_GMAC_RXCLK_DELAY_DISABLE	0
76 #define   RK3588_GMAC_RXCLK_DELAY_ENABLE	1
77 #define  RK3588_GMAC_TXCLK_DELAY_EN(id)		__BIT(2 + 2 * (id))
78 #define   RK3588_GMAC_TXCLK_DELAY_DISABLE	0
79 #define   RK3588_GMAC_TXCLK_DELAY_ENABLE	1
80 #define RK3588_GRF_GMAC_TXRX_DELAY_CFG_REG(id)	(0x0300 + (4 * 8) + (4 * (id)))
81 #define  RK3588_GMAC_RXCLK_DELAY_CFG		__BITS(15,8)
82 #define  RK3588_GMAC_TXCLK_DELAY_CFG		__BITS(7,0)
83 
84 /* grf_php */
85 #define RK3588_GRF_GMAC_PHY_REG			0x0008
86 #define  RK3588_GMAC_PHY_IFACE_SEL(id)		(__BITS(5,3) << ((id) * 6))
87 #define   RK3588_GMAC_PHY_IFACE_SEL_RGMII	1
88 #define   RK3588_GMAC_PHY_IFACE_SEL_RMII	4
89 #define RK3588_GRF_CLK_CON1			0x0070
90 #define RK3588_GRF_GMAC_CLK_REG			0x0070
91 #define  RK3588_GMAC_CLK_SELECT(id)		__BIT(4 + 5 * (id))
92 #define   RK3588_GMAC_CLK_SELECT_IO		0
93 #define   RK3588_GMAC_CLK_SELECT_CRU		1
94 #define  RK3588_GMAC_CLK_RMII_DIV(id)		__BIT(2 + 5 * (id))
95 #define   RK3588_GMA_CLK_RMII_DIV_DIV20		0
96 #define   RK3588_GMA_CLK_RMII_DIV_DIV2		1
97 #define  RK3588_GMAC_CLK_RGMII_DIV(id)		(__BITS(3,2) << ((id) * 5))
98 #define   RK3588_GMAC_CLK_RGMII_DIV_DIV1	1
99 #define   RK3588_GMAC_CLK_RGMII_DIV_DIV50	2
100 #define   RK3588_GMAC_CLK_RGMII_DIV_DIV5	3
101 #define  RK3588_GMAC_CLK_RMII_GATE_EN(id)	__BIT(1 + (id) * 5)
102 #define   RK3588_GMAC_CLK_RMII_GATE_DISABLE	0
103 #define   RK3588_GMAC_CLK_RMII_GATE_ENABLE	1
104 #define  RK3588_GMAC_CLK_MODE(id)		__BIT(0 + (id) * 5)
105 #define   RK3588_GMAC_CLK_MODE_RGMII		0
106 #define   RK3588_GMAC_CLK_MODE_RMII		1
107 
108 static void
rk3588_eqos_set_mode_rgmii(struct rk_eqos_softc * rk_sc,int tx_delay,int rx_delay)109 rk3588_eqos_set_mode_rgmii(struct rk_eqos_softc *rk_sc,
110     int tx_delay, int rx_delay)
111 {
112 	const int id = rk_sc->sc_id;
113 	uint32_t txen, rxen;
114 
115 	if (tx_delay >= 0) {
116 		txen = RK3588_GMAC_TXCLK_DELAY_ENABLE;
117 	} else {
118 		txen = RK3588_GMAC_TXCLK_DELAY_DISABLE;
119 		tx_delay = 0;
120 	}
121 	if (rx_delay >= 0) {
122 		rxen = RK3588_GMAC_RXCLK_DELAY_ENABLE;
123 	} else {
124 		rxen = RK3588_GMAC_RXCLK_DELAY_DISABLE;
125 		rx_delay = 0;
126 	}
127 
128 	syscon_lock(rk_sc->sc_grf);
129 	syscon_write_4(rk_sc->sc_grf, RK3588_GRF_GMAC_TXRXCLK_DELAY_EN_REG,
130 	    RK3588_GMAC_TXCLK_DELAY_EN(id) << 16 |		/* masks */
131 	    RK3588_GMAC_RXCLK_DELAY_EN(id) << 16 |
132 	    __SHIFTIN(txen, RK3588_GMAC_TXCLK_DELAY_EN(id)) |	/* values */
133 	    __SHIFTIN(rxen, RK3588_GMAC_RXCLK_DELAY_EN(id)));
134 	syscon_write_4(rk_sc->sc_grf, RK3588_GRF_GMAC_TXRX_DELAY_CFG_REG(id),
135 	    RK3588_GMAC_TXCLK_DELAY_CFG << 16 |			/* masks */
136 	    RK3588_GMAC_RXCLK_DELAY_CFG << 16 |
137 	    __SHIFTIN(tx_delay, RK3588_GMAC_TXCLK_DELAY_CFG) |	/* values */
138 	    __SHIFTIN(rx_delay, RK3588_GMAC_RXCLK_DELAY_CFG));
139 	syscon_unlock(rk_sc->sc_grf);
140 
141 	syscon_lock(rk_sc->sc_php_grf);
142 	syscon_write_4(rk_sc->sc_php_grf, RK3588_GRF_GMAC_PHY_REG,
143 	    RK3588_GMAC_PHY_IFACE_SEL(id) << 16 |		/* mask */
144 	    __SHIFTIN(RK3588_GMAC_PHY_IFACE_SEL_RGMII,		/* value */
145 	    RK3588_GMAC_PHY_IFACE_SEL(id)));
146 	syscon_write_4(rk_sc->sc_php_grf, RK3588_GRF_GMAC_CLK_REG,
147 	    RK3588_GMAC_CLK_MODE(id) << 16 |			/* mask */
148 	    __SHIFTIN(RK3588_GMAC_CLK_MODE_RGMII,		/* value */
149 	    RK3588_GMAC_CLK_MODE(id)));
150 	syscon_unlock(rk_sc->sc_php_grf);
151 }
152 
153 static void
rk3588_eqos_set_speed_rgmii(struct rk_eqos_softc * rk_sc,int speed)154 rk3588_eqos_set_speed_rgmii(struct rk_eqos_softc *rk_sc, int speed)
155 {
156 	const int id = rk_sc->sc_id;
157 	u_int clksel;
158 
159 	switch (speed) {
160 	case IFM_10_T:
161 		clksel = RK3588_GMAC_CLK_RGMII_DIV_DIV50;
162 		break;
163 	case IFM_100_TX:
164 		clksel = RK3588_GMAC_CLK_RGMII_DIV_DIV5;
165 		break;
166 	case IFM_1000_T:
167 	default:
168 		clksel = RK3588_GMAC_CLK_RGMII_DIV_DIV1;
169 		break;
170 	}
171 
172 	syscon_lock(rk_sc->sc_php_grf);
173 	syscon_write_4(rk_sc->sc_php_grf, RK3588_GRF_GMAC_CLK_REG,
174 	    RK3588_GMAC_CLK_RGMII_DIV(id) << 16 |		/* mask */
175 	    __SHIFTIN(clksel, RK3588_GMAC_CLK_RGMII_DIV(id)));	/* value */
176 	syscon_unlock(rk_sc->sc_php_grf);
177 }
178 
179 static void
rk3588_eqos_clock_selection(struct rk_eqos_softc * rk_sc,int phandle)180 rk3588_eqos_clock_selection(struct rk_eqos_softc *rk_sc, int phandle)
181 {
182 	const int id = rk_sc->sc_id;
183 	const char *clock_in_out;
184 
185 	clock_in_out = fdtbus_get_string(phandle, "clock_in_out");
186 	if (clock_in_out != NULL) {
187 		bool input = (strcmp(clock_in_out, "input") == 0) ?
188 		    true : false;
189 		uint32_t clksel, gate;
190 
191 		if (input) {
192 			clksel = RK3588_GMAC_CLK_SELECT_IO;
193 			gate = RK3588_GMAC_CLK_RMII_GATE_DISABLE;
194 		} else {
195 			clksel = RK3588_GMAC_CLK_SELECT_CRU;
196 			gate = RK3588_GMAC_CLK_RMII_GATE_ENABLE;
197 		}
198 
199 		syscon_lock(rk_sc->sc_php_grf);
200 		syscon_write_4(rk_sc->sc_php_grf, RK3588_GRF_GMAC_CLK_REG,
201 		    /* masks */
202 		    RK3588_GMAC_CLK_SELECT(id) << 16 |
203 		    RK3588_GMAC_CLK_RMII_GATE_EN(id) << 16 |
204 		    /* values */
205 		    __SHIFTIN(clksel, RK3588_GMAC_CLK_SELECT(id)) |
206 		    __SHIFTIN(gate, RK3588_GMAC_CLK_RMII_GATE_EN(id)));
207 		syscon_unlock(rk_sc->sc_php_grf);
208 	}
209 }
210 
211 static int
rk3588_eqos_get_unit(struct rk_eqos_softc * rk_sc,int phandle)212 rk3588_eqos_get_unit(struct rk_eqos_softc *rk_sc, int phandle)
213 {
214 	bus_addr_t addr;
215 	bus_size_t size;
216 
217 	fdtbus_get_reg(phandle, 0, &addr, &size);
218 	if (addr == RK3588_ETHERNET1_ADDR)
219 		return 1;
220 	return 0;
221 }
222 
223 static const struct rk_eqos_ops rk3588_ops = {
224 	.set_mode_rgmii = rk3588_eqos_set_mode_rgmii,
225 	.set_speed_rgmii = rk3588_eqos_set_speed_rgmii,
226 	.clock_selection = rk3588_eqos_clock_selection,
227 	.get_unit = rk3588_eqos_get_unit
228 };
229 
230 static const struct device_compatible_entry compat_data[] = {
231 	{ .compat = "rockchip,rk3588-gmac", .value = (uintptr_t)&rk3588_ops },
232 	DEVICE_COMPAT_EOL
233 };
234 
235 static int
rk_eqos_reset_gpio(const int phandle)236 rk_eqos_reset_gpio(const int phandle)
237 {
238 	struct fdtbus_gpio_pin *pin_reset;
239 	const u_int *reset_delay_us;
240 	bool reset_active_low;
241 	int len;
242 
243 	if (!of_hasprop(phandle, "snps,reset-gpio"))
244 		return 0;
245 
246 	pin_reset = fdtbus_gpio_acquire(phandle, "snps,reset-gpio",
247 	    GPIO_PIN_OUTPUT);
248 	if (pin_reset == NULL)
249 		return ENOENT;
250 
251 	reset_delay_us = fdtbus_get_prop(phandle, "snps,reset-delays-us", &len);
252 	if (reset_delay_us == NULL || len != 12)
253 		return ENXIO;
254 
255 	reset_active_low = of_hasprop(phandle, "snps,reset-active-low");
256 
257 	fdtbus_gpio_write_raw(pin_reset, reset_active_low ? 1 : 0);
258 	delay(be32toh(reset_delay_us[0]));
259 	fdtbus_gpio_write_raw(pin_reset, reset_active_low ? 0 : 1);
260 	delay(be32toh(reset_delay_us[1]));
261 	fdtbus_gpio_write_raw(pin_reset, reset_active_low ? 1 : 0);
262 	delay(be32toh(reset_delay_us[2]));
263 
264 	return 0;
265 }
266 
267 static void
rk_eqos_init_props(struct eqos_softc * sc,int phandle)268 rk_eqos_init_props(struct eqos_softc *sc, int phandle)
269 {
270 	prop_dictionary_t prop = device_properties(sc->sc_dev);
271 
272 	/* Defaults */
273 	prop_dictionary_set_uint(prop, "snps,wr_osr_lmt", 4);
274 	prop_dictionary_set_uint(prop, "snps,rd_osr_lmt", 8);
275 
276 	if (of_hasprop(phandle, "snps,mixed-burst"))
277 		prop_dictionary_set_bool(prop, "snps,mixed-burst", true);
278 	if (of_hasprop(phandle, "snps,tso"))
279 		prop_dictionary_set_bool(prop, "snps,tso", true);
280 }
281 
282 static int
rk_eqos_match(device_t parent,cfdata_t cf,void * aux)283 rk_eqos_match(device_t parent, cfdata_t cf, void *aux)
284 {
285 	struct fdt_attach_args * const faa = aux;
286 
287 	return of_compatible_match(faa->faa_phandle, compat_data);
288 }
289 
290 static void
rk_eqos_attach(device_t parent,device_t self,void * aux)291 rk_eqos_attach(device_t parent, device_t self, void *aux)
292 {
293 	struct rk_eqos_softc * const rk_sc = device_private(self);
294 	struct eqos_softc * const sc = &rk_sc->sc_base;
295 	struct fdt_attach_args * const faa = aux;
296 	const int phandle = faa->faa_phandle;
297 	const char *phy_mode;
298 	char intrstr[128];
299 	bus_addr_t addr;
300 	bus_size_t size;
301 	u_int tx_delay, rx_delay;
302 	int n;
303 
304 	struct rk_eqos_ops *ops = (struct rk_eqos_ops *)
305 	    of_compatible_lookup(phandle, compat_data)->value;
306 
307 	/* multiple ethernet? */
308 	if (ops->get_unit != NULL)
309 		rk_sc->sc_id = ops->get_unit(rk_sc, phandle);
310 
311 	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
312 		aprint_error(": couldn't get registers\n");
313 		return;
314 	}
315 
316 	rk_sc->sc_grf = fdtbus_syscon_acquire(phandle, "rockchip,grf");
317 	if (rk_sc->sc_grf == NULL) {
318 		aprint_error(": couldn't get grf syscon\n");
319 		return;
320 	}
321 	rk_sc->sc_php_grf = fdtbus_syscon_acquire(phandle, "rockchip,php_grf");
322 	if (rk_sc->sc_php_grf == NULL) {
323 		aprint_error(": couldn't get php_grf syscon\n");
324 		return;
325 	}
326 
327 	sc->sc_dev = self;
328 	sc->sc_bst = faa->faa_bst;
329 	if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
330 		aprint_error(": couldn't map registers\n");
331 		return;
332 	}
333 	sc->sc_dmat = faa->faa_dmat;
334 
335 	if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) {
336 		aprint_error(": failed to decode interrupt\n");
337 		return;
338 	}
339 
340 	/* enable clocks */
341 	struct clk *clk;
342 	fdtbus_clock_assign(phandle);
343 	for (n = 0; (clk = fdtbus_clock_get_index(phandle, n)) != NULL; n++) {
344 		if (clk_enable(clk) != 0) {
345 			aprint_error(": couldn't enable clock #%d\n", n);
346 			return;
347 		}
348 	}
349 	/* de-assert resets */
350 	struct fdtbus_reset *rst;
351 	for (n = 0; (rst = fdtbus_reset_get_index(phandle, n)) != NULL; n++) {
352 		if (fdtbus_reset_deassert(rst) != 0) {
353 			aprint_error(": couldn't de-assert reset #%d\n", n);
354 			return;
355 		}
356 	}
357 	if (rk_eqos_reset_gpio(phandle) != 0)
358 		aprint_error(": GPIO reset failed\n");	/* ignore */
359 
360 	if (ops->clock_selection != NULL)
361 		ops->clock_selection(rk_sc, phandle);
362 
363 	if (of_getprop_uint32(phandle, "tx_delay", &tx_delay) != 0)
364 		tx_delay = -1;
365 	if (of_getprop_uint32(phandle, "rx_delay", &rx_delay) != 0)
366 		rx_delay = -1;
367 
368 	phy_mode = fdtbus_get_string(phandle, "phy-mode");
369 	if (phy_mode == NULL)
370 		phy_mode = "rgmii";	/* default: RGMII */
371 
372 	if (strncmp(phy_mode, "rgmii", 5) == 0) {
373 		ops->set_mode_rgmii(rk_sc, tx_delay, rx_delay);
374 		if (ops->set_speed_rgmii != NULL) {
375 			/*
376 			 * XXX: should be called back from
377 			 *  sys/dev/ic/dwc_eqos.c:eqos_update_link() ?
378 			 */
379 			ops->set_speed_rgmii(rk_sc, IFM_1000_T);
380 		}
381 	} else {
382 		aprint_error(": unsupported phy-mode '%s'\n", phy_mode);
383 		return;
384 	}
385 
386 	rk_eqos_init_props(sc, phandle);
387 	sc->sc_phy_id = MII_PHY_ANY;
388 #define CSR_RATE_RGMII	125000000	/* default */
389 	sc->sc_csr_clock = CSR_RATE_RGMII;
390 
391 	if (eqos_attach(sc) != 0)
392 		return;
393 
394 	if (fdtbus_intr_establish_xname(phandle, 0, IPL_NET, FDT_INTR_MPSAFE,
395 	    eqos_intr, sc, device_xname(self)) == NULL) {
396 		aprint_error_dev(self, "failed to establish interrupt on %s\n",
397 		    intrstr);
398 		return;
399 	}
400 	aprint_normal_dev(self, "interrupting on %s\n", intrstr);
401 }
402