xref: /netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/radeon_evergreen_blit_shaders.c (revision 41ec02673d281bbb3d38e6c78504ce6e30c228c1)
1 /*	$NetBSD: radeon_evergreen_blit_shaders.c,v 1.2 2021/12/18 23:45:43 riastradh Exp $	*/
2 
3 /*
4  * Copyright 2010 Advanced Micro Devices, Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice (including the next
14  * paragraph) shall be included in all copies or substantial portions of the
15  * Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
20  * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23  * DEALINGS IN THE SOFTWARE.
24  *
25  * Authors:
26  *     Alex Deucher <alexander.deucher@amd.com>
27  */
28 
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: radeon_evergreen_blit_shaders.c,v 1.2 2021/12/18 23:45:43 riastradh Exp $");
31 
32 #include <linux/bug.h>
33 #include <linux/types.h>
34 #include <linux/kernel.h>
35 
36 /*
37  * evergreen cards need to use the 3D engine to blit data which requires
38  * quite a bit of hw state setup.  Rather than pull the whole 3D driver
39  * (which normally generates the 3D state) into the DRM, we opt to use
40  * statically generated state tables.  The register state and shaders
41  * were hand generated to support blitting functionality.  See the 3D
42  * driver or documentation for descriptions of the registers and
43  * shader instructions.
44  */
45 
46 const u32 evergreen_default_state[] =
47 {
48 	0xc0016900,
49 	0x0000023b,
50 	0x00000000, /* SQ_LDS_ALLOC_PS */
51 
52 	0xc0066900,
53 	0x00000240,
54 	0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
55 	0x00000000,
56 	0x00000000,
57 	0x00000000,
58 	0x00000000,
59 	0x00000000,
60 
61 	0xc0046900,
62 	0x00000247,
63 	0x00000000, /* SQ_GS_VERT_ITEMSIZE */
64 	0x00000000,
65 	0x00000000,
66 	0x00000000,
67 
68 	0xc0026900,
69 	0x00000010,
70 	0x00000000, /* DB_Z_INFO */
71 	0x00000000, /* DB_STENCIL_INFO */
72 
73 	0xc0016900,
74 	0x00000200,
75 	0x00000000, /* DB_DEPTH_CONTROL */
76 
77 	0xc0066900,
78 	0x00000000,
79 	0x00000060, /* DB_RENDER_CONTROL */
80 	0x00000000, /* DB_COUNT_CONTROL */
81 	0x00000000, /* DB_DEPTH_VIEW */
82 	0x0000002a, /* DB_RENDER_OVERRIDE */
83 	0x00000000, /* DB_RENDER_OVERRIDE2 */
84 	0x00000000, /* DB_HTILE_DATA_BASE */
85 
86 	0xc0026900,
87 	0x0000000a,
88 	0x00000000, /* DB_STENCIL_CLEAR */
89 	0x00000000, /* DB_DEPTH_CLEAR */
90 
91 	0xc0016900,
92 	0x000002dc,
93 	0x0000aa00, /* DB_ALPHA_TO_MASK */
94 
95 	0xc0016900,
96 	0x00000080,
97 	0x00000000, /* PA_SC_WINDOW_OFFSET */
98 
99 	0xc00d6900,
100 	0x00000083,
101 	0x0000ffff, /* PA_SC_CLIPRECT_RULE */
102 	0x00000000, /* PA_SC_CLIPRECT_0_TL */
103 	0x20002000, /* PA_SC_CLIPRECT_0_BR */
104 	0x00000000,
105 	0x20002000,
106 	0x00000000,
107 	0x20002000,
108 	0x00000000,
109 	0x20002000,
110 	0xaaaaaaaa, /* PA_SC_EDGERULE */
111 	0x00000000, /* PA_SU_HARDWARE_SCREEN_OFFSET */
112 	0x0000000f, /* CB_TARGET_MASK */
113 	0x0000000f, /* CB_SHADER_MASK */
114 
115 	0xc0226900,
116 	0x00000094,
117 	0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
118 	0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
119 	0x80000000,
120 	0x20002000,
121 	0x80000000,
122 	0x20002000,
123 	0x80000000,
124 	0x20002000,
125 	0x80000000,
126 	0x20002000,
127 	0x80000000,
128 	0x20002000,
129 	0x80000000,
130 	0x20002000,
131 	0x80000000,
132 	0x20002000,
133 	0x80000000,
134 	0x20002000,
135 	0x80000000,
136 	0x20002000,
137 	0x80000000,
138 	0x20002000,
139 	0x80000000,
140 	0x20002000,
141 	0x80000000,
142 	0x20002000,
143 	0x80000000,
144 	0x20002000,
145 	0x80000000,
146 	0x20002000,
147 	0x80000000,
148 	0x20002000,
149 	0x00000000, /* PA_SC_VPORT_ZMIN_0 */
150 	0x3f800000, /* PA_SC_VPORT_ZMAX_0 */
151 
152 	0xc0016900,
153 	0x000000d4,
154 	0x00000000, /* SX_MISC */
155 
156 	0xc0026900,
157 	0x00000292,
158 	0x00000000, /* PA_SC_MODE_CNTL_0 */
159 	0x00000000, /* PA_SC_MODE_CNTL_1 */
160 
161 	0xc0106900,
162 	0x00000300,
163 	0x00000000, /* PA_SC_LINE_CNTL */
164 	0x00000000, /* PA_SC_AA_CONFIG */
165 	0x00000005, /* PA_SU_VTX_CNTL */
166 	0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
167 	0x3f800000, /* PA_CL_GB_VERT_DISC_ADJ */
168 	0x3f800000, /* PA_CL_GB_HORZ_CLIP_ADJ */
169 	0x3f800000, /* PA_CL_GB_HORZ_DISC_ADJ */
170 	0x00000000, /* PA_SC_AA_SAMPLE_LOCS_0 */
171 	0x00000000, /*  */
172 	0x00000000, /*  */
173 	0x00000000, /*  */
174 	0x00000000, /*  */
175 	0x00000000, /*  */
176 	0x00000000, /*  */
177 	0x00000000, /* PA_SC_AA_SAMPLE_LOCS_7 */
178 	0xffffffff, /* PA_SC_AA_MASK */
179 
180 	0xc00d6900,
181 	0x00000202,
182 	0x00cc0010, /* CB_COLOR_CONTROL */
183 	0x00000210, /* DB_SHADER_CONTROL */
184 	0x00010000, /* PA_CL_CLIP_CNTL */
185 	0x00000004, /* PA_SU_SC_MODE_CNTL */
186 	0x00000100, /* PA_CL_VTE_CNTL */
187 	0x00000000, /* PA_CL_VS_OUT_CNTL */
188 	0x00000000, /* PA_CL_NANINF_CNTL */
189 	0x00000000, /* PA_SU_LINE_STIPPLE_CNTL */
190 	0x00000000, /* PA_SU_LINE_STIPPLE_SCALE */
191 	0x00000000, /* PA_SU_PRIM_FILTER_CNTL */
192 	0x00000000, /*  */
193 	0x00000000, /*  */
194 	0x00000000, /* SQ_DYN_GPR_RESOURCE_LIMIT_1 */
195 
196 	0xc0066900,
197 	0x000002de,
198 	0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
199 	0x00000000, /*  */
200 	0x00000000, /*  */
201 	0x00000000, /*  */
202 	0x00000000, /*  */
203 	0x00000000, /*  */
204 
205 	0xc0016900,
206 	0x00000229,
207 	0x00000000, /* SQ_PGM_START_FS */
208 
209 	0xc0016900,
210 	0x0000022a,
211 	0x00000000, /* SQ_PGM_RESOURCES_FS */
212 
213 	0xc0096900,
214 	0x00000100,
215 	0x00ffffff, /* VGT_MAX_VTX_INDX */
216 	0x00000000, /*  */
217 	0x00000000, /*  */
218 	0x00000000, /*  */
219 	0x00000000, /* SX_ALPHA_TEST_CONTROL */
220 	0x00000000, /* CB_BLEND_RED */
221 	0x00000000, /* CB_BLEND_GREEN */
222 	0x00000000, /* CB_BLEND_BLUE */
223 	0x00000000, /* CB_BLEND_ALPHA */
224 
225 	0xc0026900,
226 	0x000002a8,
227 	0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
228 	0x00000000, /*  */
229 
230 	0xc0026900,
231 	0x000002ad,
232 	0x00000000, /* VGT_REUSE_OFF */
233 	0x00000000, /*  */
234 
235 	0xc0116900,
236 	0x00000280,
237 	0x00000000, /* PA_SU_POINT_SIZE */
238 	0x00000000, /* PA_SU_POINT_MINMAX */
239 	0x00000008, /* PA_SU_LINE_CNTL */
240 	0x00000000, /* PA_SC_LINE_STIPPLE */
241 	0x00000000, /* VGT_OUTPUT_PATH_CNTL */
242 	0x00000000, /* VGT_HOS_CNTL */
243 	0x00000000, /*  */
244 	0x00000000, /*  */
245 	0x00000000, /*  */
246 	0x00000000, /*  */
247 	0x00000000, /*  */
248 	0x00000000, /*  */
249 	0x00000000, /*  */
250 	0x00000000, /*  */
251 	0x00000000, /*  */
252 	0x00000000, /*  */
253 	0x00000000, /* VGT_GS_MODE */
254 
255 	0xc0016900,
256 	0x000002a1,
257 	0x00000000, /* VGT_PRIMITIVEID_EN */
258 
259 	0xc0016900,
260 	0x000002a5,
261 	0x00000000, /* VGT_MULTI_PRIM_IB_RESET_EN */
262 
263 	0xc0016900,
264 	0x000002d5,
265 	0x00000000, /* VGT_SHADER_STAGES_EN */
266 
267 	0xc0026900,
268 	0x000002e5,
269 	0x00000000, /* VGT_STRMOUT_CONFIG */
270 	0x00000000, /*  */
271 
272 	0xc0016900,
273 	0x000001e0,
274 	0x00000000, /* CB_BLEND0_CONTROL */
275 
276 	0xc0016900,
277 	0x000001b1,
278 	0x00000000, /* SPI_VS_OUT_CONFIG */
279 
280 	0xc0016900,
281 	0x00000187,
282 	0x00000000, /* SPI_VS_OUT_ID_0 */
283 
284 	0xc0016900,
285 	0x00000191,
286 	0x00000100, /* SPI_PS_INPUT_CNTL_0 */
287 
288 	0xc00b6900,
289 	0x000001b3,
290 	0x20000001, /* SPI_PS_IN_CONTROL_0 */
291 	0x00000000, /* SPI_PS_IN_CONTROL_1 */
292 	0x00000000, /* SPI_INTERP_CONTROL_0 */
293 	0x00000000, /* SPI_INPUT_Z */
294 	0x00000000, /* SPI_FOG_CNTL */
295 	0x00100000, /* SPI_BARYC_CNTL */
296 	0x00000000, /* SPI_PS_IN_CONTROL_2 */
297 	0x00000000, /*  */
298 	0x00000000, /*  */
299 	0x00000000, /*  */
300 	0x00000000, /*  */
301 
302 	0xc0026900,
303 	0x00000316,
304 	0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */
305 	0x00000010, /*  */
306 };
307 
308 const u32 evergreen_default_size = ARRAY_SIZE(evergreen_default_state);
309