1 /* $NetBSD: pyro.c,v 1.26 2022/01/21 19:14:14 thorpej Exp $ */
2 /* from: $OpenBSD: pyro.c,v 1.20 2010/12/05 15:15:14 kettenis Exp $ */
3
4 /*
5 * Copyright (c) 2002 Jason L. Wright (jason@thought.net)
6 * Copyright (c) 2003 Henric Jungheim
7 * Copyright (c) 2007 Mark Kettenis
8 * Copyright (c) 2011 Matthew R. Green
9 * All rights reserved.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
23 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
24 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
25 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
26 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
28 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
29 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 __KERNEL_RCSID(0, "$NetBSD: pyro.c,v 1.26 2022/01/21 19:14:14 thorpej Exp $");
35
36 #include <sys/param.h>
37 #include <sys/device.h>
38 #include <sys/errno.h>
39 #include <sys/malloc.h>
40 #include <sys/kmem.h>
41 #include <sys/systm.h>
42
43 #define _SPARC_BUS_DMA_PRIVATE
44 #include <sys/bus.h>
45 #include <machine/autoconf.h>
46
47 #ifdef DDB
48 #include <machine/db_machdep.h>
49 #endif
50
51 #include <dev/pci/pcivar.h>
52 #include <dev/pci/pcireg.h>
53
54 #include <sparc64/dev/iommureg.h>
55 #include <sparc64/dev/iommuvar.h>
56 #include <sparc64/dev/pyrovar.h>
57
58 #ifdef DEBUG
59 #define PDB_PROM 0x01
60 #define PDB_BUSMAP 0x02
61 #define PDB_INTR 0x04
62 #define PDB_CONF 0x08
63 int pyro_debug = 0x0;
64 #define DPRINTF(l, s) do { if (pyro_debug & l) printf s; } while (0)
65 #else
66 #define DPRINTF(l, s)
67 #endif
68
69 #define FIRE_RESET_GEN 0x7010
70
71 #define FIRE_RESET_GEN_XIR 0x0000000000000002L
72
73 #define FIRE_INTRMAP_INT_CNTRL_NUM_MASK 0x000003c0
74 #define FIRE_INTRMAP_INT_CNTRL_NUM0 0x00000040
75 #define FIRE_INTRMAP_INT_CNTRL_NUM1 0x00000080
76 #define FIRE_INTRMAP_INT_CNTRL_NUM2 0x00000100
77 #define FIRE_INTRMAP_INT_CNTRL_NUM3 0x00000200
78 #define FIRE_INTRMAP_T_JPID_SHIFT 26
79 #define FIRE_INTRMAP_T_JPID_MASK 0x7c000000
80
81 #define OBERON_INTRMAP_T_DESTID_SHIFT 21
82 #define OBERON_INTRMAP_T_DESTID_MASK 0x7fe00000
83
84 extern struct sparc_pci_chipset _sparc_pci_chipset;
85
86 int pyro_match(device_t, cfdata_t, void *);
87 void pyro_attach(device_t, device_t, void *);
88 int pyro_print(void *, const char *);
89
90 CFATTACH_DECL_NEW(pyro, sizeof(struct pyro_softc),
91 pyro_match, pyro_attach, NULL, NULL);
92
93 void pyro_init(struct pyro_softc *, int);
94 void pyro_init_iommu(struct pyro_softc *, struct pyro_pbm *);
95
96 pci_chipset_tag_t pyro_alloc_chipset(struct pyro_pbm *, int,
97 pci_chipset_tag_t);
98 bus_space_tag_t pyro_alloc_mem_tag(struct pyro_pbm *);
99 bus_space_tag_t pyro_alloc_io_tag(struct pyro_pbm *);
100 bus_space_tag_t pyro_alloc_config_tag(struct pyro_pbm *);
101 bus_space_tag_t pyro_alloc_bus_tag(struct pyro_pbm *, const char *, int);
102 bus_dma_tag_t pyro_alloc_dma_tag(struct pyro_pbm *);
103
104 #if 0
105 int pyro_conf_size(pci_chipset_tag_t, pcitag_t);
106 #endif
107 pcireg_t pyro_conf_read(pci_chipset_tag_t, pcitag_t, int);
108 void pyro_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t);
109
110 static void * pyro_pci_intr_establish(pci_chipset_tag_t pc,
111 pci_intr_handle_t ih, int level,
112 int (*func)(void *), void *arg);
113
114 int pyro_intr_map(const struct pci_attach_args *, pci_intr_handle_t *);
115 int pyro_bus_map(bus_space_tag_t, bus_addr_t,
116 bus_size_t, int, vaddr_t, bus_space_handle_t *);
117 paddr_t pyro_bus_mmap(bus_space_tag_t, bus_addr_t, off_t,
118 int, int);
119 void *pyro_intr_establish(bus_space_tag_t, int, int,
120 int (*)(void *), void *, void (*)(void));
121
122 int pyro_dmamap_create(bus_dma_tag_t, bus_size_t, int,
123 bus_size_t, bus_size_t, int, bus_dmamap_t *);
124
125 int
pyro_match(device_t parent,cfdata_t match,void * aux)126 pyro_match(device_t parent, cfdata_t match, void *aux)
127 {
128 struct mainbus_attach_args *ma = aux;
129 char *str;
130
131 if (strcmp(ma->ma_name, "pci") != 0)
132 return (0);
133
134 str = prom_getpropstring(ma->ma_node, "compatible");
135 if (strcmp(str, "pciex108e,80f0") == 0 ||
136 strcmp(str, "pciex108e,80f8") == 0)
137 return (1);
138
139 return (0);
140 }
141
142 void
pyro_attach(device_t parent,device_t self,void * aux)143 pyro_attach(device_t parent, device_t self, void *aux)
144 {
145 struct pyro_softc *sc = device_private(self);
146 struct mainbus_attach_args *ma = aux;
147 char *str;
148 int busa;
149
150 sc->sc_dev = self;
151 sc->sc_node = ma->ma_node;
152 sc->sc_dmat = ma->ma_dmatag;
153 sc->sc_bustag = ma->ma_bustag;
154 sc->sc_csr = ma->ma_reg[0].ur_paddr;
155 sc->sc_xbc = ma->ma_reg[1].ur_paddr;
156 sc->sc_ign = INTIGN(ma->ma_upaid << INTMAP_IGN_SHIFT);
157
158 if ((ma->ma_reg[0].ur_paddr & 0x00700000) == 0x00600000)
159 busa = 1;
160 else
161 busa = 0;
162
163 if (bus_space_map(sc->sc_bustag, sc->sc_csr,
164 ma->ma_reg[0].ur_len, BUS_SPACE_MAP_LINEAR, &sc->sc_csrh)) {
165 printf(": failed to map csr registers\n");
166 return;
167 }
168
169 if (bus_space_map(sc->sc_bustag, sc->sc_xbc,
170 ma->ma_reg[1].ur_len, 0, &sc->sc_xbch)) {
171 printf(": failed to map xbc registers\n");
172 return;
173 }
174
175 str = prom_getpropstring(ma->ma_node, "compatible");
176 if (strcmp(str, "pciex108e,80f8") == 0)
177 sc->sc_oberon = 1;
178
179 pyro_init(sc, busa);
180 }
181
182 void
pyro_init(struct pyro_softc * sc,int busa)183 pyro_init(struct pyro_softc *sc, int busa)
184 {
185 struct pyro_pbm *pbm;
186 struct pcibus_attach_args pba;
187 int *busranges = NULL, nranges;
188
189 pbm = kmem_zalloc(sizeof(*pbm), KM_SLEEP);
190 pbm->pp_sc = sc;
191 pbm->pp_bus_a = busa;
192
193 if (prom_getprop(sc->sc_node, "ranges", sizeof(struct pyro_range),
194 &pbm->pp_nrange, (void **)&pbm->pp_range))
195 panic("pyro: can't get ranges");
196
197 if (prom_getprop(sc->sc_node, "bus-range", sizeof(int), &nranges,
198 (void **)&busranges))
199 panic("pyro: can't get bus-range");
200
201 printf(": \"%s\", rev %d, ign %x, bus %c %d to %d\n",
202 sc->sc_oberon ? "Oberon" : "Fire",
203 prom_getpropint(sc->sc_node, "module-revision#", 0), sc->sc_ign,
204 busa ? 'A' : 'B', busranges[0], busranges[1]);
205
206 printf("%s: ", device_xname(sc->sc_dev));
207 pyro_init_iommu(sc, pbm);
208
209 pbm->pp_memt = pyro_alloc_mem_tag(pbm);
210 pbm->pp_iot = pyro_alloc_io_tag(pbm);
211 pbm->pp_cfgt = pyro_alloc_config_tag(pbm);
212 pbm->pp_dmat = pyro_alloc_dma_tag(pbm);
213 pbm->pp_flags = (pbm->pp_memt ? PCI_FLAGS_MEM_OKAY : 0) |
214 (pbm->pp_iot ? PCI_FLAGS_IO_OKAY : 0);
215
216 if (bus_space_map(pbm->pp_cfgt, 0, 0x10000000, 0, &pbm->pp_cfgh))
217 panic("pyro: can't map config space");
218
219 pbm->pp_pc = pyro_alloc_chipset(pbm, sc->sc_node, &_sparc_pci_chipset);
220 pbm->pp_pc->spc_busmax = busranges[1];
221 pbm->pp_pc->spc_busnode = kmem_zalloc(sizeof(*pbm->pp_pc->spc_busnode),
222 KM_SLEEP);
223
224 #if 0
225 pbm->pp_pc->bustag = pbm->pp_cfgt;
226 pbm->pp_pc->bushandle = pbm->pp_cfgh;
227 #endif
228
229 bzero(&pba, sizeof(pba));
230 pba.pba_bus = busranges[0];
231 pba.pba_pc = pbm->pp_pc;
232 pba.pba_flags = pbm->pp_flags;
233 pba.pba_dmat = pbm->pp_dmat;
234 pba.pba_dmat64 = NULL; /* XXX */
235 pba.pba_memt = pbm->pp_memt;
236 pba.pba_iot = pbm->pp_iot;
237
238 free(busranges, M_DEVBUF);
239
240 config_found(sc->sc_dev, &pba, pyro_print,
241 CFARGS(.devhandle = device_handle(sc->sc_dev)));
242 }
243
244 void
pyro_init_iommu(struct pyro_softc * sc,struct pyro_pbm * pbm)245 pyro_init_iommu(struct pyro_softc *sc, struct pyro_pbm *pbm)
246 {
247 struct iommu_state *is = &pbm->pp_is;
248 int tsbsize = 7;
249 u_int32_t iobase = -1;
250 char *name;
251
252 pbm->pp_sb.sb_is = is;
253 is->is_bustag = sc->sc_bustag;
254
255 if (bus_space_subregion(is->is_bustag, sc->sc_csrh,
256 0x40000, 0x100, &is->is_iommu)) {
257 panic("pyro: unable to create iommu handle");
258 }
259
260 /* We have no STC. */
261 is->is_sb[0] = NULL;
262
263 name = kmem_asprintf("%s dvma", device_xname(sc->sc_dev));
264
265 /* Tell iommu how to set the TSB size. */
266 is->is_flags = IOMMU_TSBSIZE_IN_PTSB;
267
268 /* On Oberon, we need to flush the cache. */
269 if (sc->sc_oberon)
270 is->is_flags |= IOMMU_FLUSH_CACHE;
271
272 iommu_init(name, is, tsbsize, iobase);
273 }
274
275 int
pyro_print(void * aux,const char * p)276 pyro_print(void *aux, const char *p)
277 {
278 if (p == NULL)
279 return (UNCONF);
280 return (QUIET);
281 }
282
283 pcireg_t
pyro_conf_read(pci_chipset_tag_t pc,pcitag_t tag,int reg)284 pyro_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
285 {
286 struct pyro_pbm *pp = pc->cookie;
287 pcireg_t val = (pcireg_t)~0;
288 int s;
289
290 DPRINTF(PDB_CONF, ("%s: tag %lx reg %x ", __func__, (long)tag, reg));
291 if (PCITAG_NODE(tag) != -1 && (unsigned int)reg < PCI_CONF_SIZE) {
292 s = splhigh();
293 struct cpu_info *ci = curcpu();
294 ci->ci_pci_probe = true;
295 membar_Sync();
296 val = bus_space_read_4(pp->pp_cfgt, pp->pp_cfgh,
297 (PCITAG_OFFSET(tag) << 4) + reg);
298 membar_Sync();
299 if (ci->ci_pci_fault)
300 val = (pcireg_t)~0;
301 ci->ci_pci_probe = ci->ci_pci_fault = false;
302 splx(s);
303 }
304 DPRINTF(PDB_CONF, (" returning %08x\n", (u_int)val));
305 return (val);
306 }
307
308 void
pyro_conf_write(pci_chipset_tag_t pc,pcitag_t tag,int reg,pcireg_t data)309 pyro_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
310 {
311 struct pyro_pbm *pp = pc->cookie;
312
313 DPRINTF(PDB_CONF, ("%s: tag %lx; reg %x; data %x", __func__,
314 (long)tag, reg, (int)data));
315
316 /* If we don't know it, just punt it. */
317 if (PCITAG_NODE(tag) == -1) {
318 DPRINTF(PDB_CONF, (" .. bad addr\n"));
319 return;
320 }
321
322 if ((unsigned int)reg >= PCI_CONF_SIZE)
323 return;
324
325 bus_space_write_4(pp->pp_cfgt, pp->pp_cfgh,
326 (PCITAG_OFFSET(tag) << 4) + reg, data);
327 DPRINTF(PDB_CONF, (" .. done\n"));
328 }
329
330 /*
331 * Bus-specific interrupt mapping
332 */
333 int
pyro_intr_map(const struct pci_attach_args * pa,pci_intr_handle_t * ihp)334 pyro_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
335 {
336 struct pyro_pbm *pp = pa->pa_pc->cookie;
337 struct pyro_softc *sc = pp->pp_sc;
338 u_int dev;
339
340 if (*ihp != (pci_intr_handle_t)-1) {
341 *ihp |= sc->sc_ign;
342 DPRINTF(PDB_INTR, ("%s: not -1 -> ih %lx\n", __func__, (u_long)*ihp));
343 return (0);
344 }
345
346 /*
347 * We didn't find a PROM mapping for this interrupt. Try to
348 * construct one ourselves based on the swizzled interrupt pin
349 * and the interrupt mapping for PCI slots documented in the
350 * UltraSPARC-IIi User's Manual.
351 */
352
353 if (pa->pa_intrpin == 0) {
354 DPRINTF(PDB_INTR, ("%s: no intrpen\n", __func__));
355 return (-1);
356 }
357
358 /*
359 * This deserves some documentation. Should anyone
360 * have anything official looking, please speak up.
361 */
362 dev = pa->pa_device - 1;
363
364 *ihp = (pa->pa_intrpin - 1) & INTMAP_PCIINT;
365 *ihp |= (dev << 2) & INTMAP_PCISLOT;
366 *ihp |= sc->sc_ign;
367
368 DPRINTF(PDB_INTR, ("%s: weird hack -> ih %lx\n", __func__, (u_long)*ihp));
369 return (0);
370 }
371
372 bus_space_tag_t
pyro_alloc_mem_tag(struct pyro_pbm * pp)373 pyro_alloc_mem_tag(struct pyro_pbm *pp)
374 {
375 return (pyro_alloc_bus_tag(pp, "mem", PCI_MEMORY_BUS_SPACE));
376 }
377
378 bus_space_tag_t
pyro_alloc_io_tag(struct pyro_pbm * pp)379 pyro_alloc_io_tag(struct pyro_pbm *pp)
380 {
381 return (pyro_alloc_bus_tag(pp, "io", PCI_IO_BUS_SPACE));
382 }
383
384 bus_space_tag_t
pyro_alloc_config_tag(struct pyro_pbm * pp)385 pyro_alloc_config_tag(struct pyro_pbm *pp)
386 {
387 return (pyro_alloc_bus_tag(pp, "cfg", PCI_CONFIG_BUS_SPACE));
388 }
389
390 bus_space_tag_t
pyro_alloc_bus_tag(struct pyro_pbm * pbm,const char * name,int type)391 pyro_alloc_bus_tag(struct pyro_pbm *pbm, const char *name, int type)
392 {
393 struct pyro_softc *sc = pbm->pp_sc;
394 struct sparc_bus_space_tag *bt;
395
396 bt = kmem_zalloc(sizeof(*bt), KM_SLEEP);
397
398 #if 0
399 snprintf(bt->name, sizeof(bt->name), "%s-pbm_%s(%d/%2.2x)",
400 device_xname(sc->sc_dev), name, ss, asi);
401 #endif
402
403 bt->cookie = pbm;
404 bt->parent = sc->sc_bustag;
405 bt->type = type;
406 bt->sparc_bus_map = pyro_bus_map;
407 bt->sparc_bus_mmap = pyro_bus_mmap;
408 bt->sparc_intr_establish = pyro_intr_establish;
409 return (bt);
410 }
411
412 bus_dma_tag_t
pyro_alloc_dma_tag(struct pyro_pbm * pbm)413 pyro_alloc_dma_tag(struct pyro_pbm *pbm)
414 {
415 struct pyro_softc *sc = pbm->pp_sc;
416 bus_dma_tag_t dt, pdt = sc->sc_dmat;
417
418 dt = kmem_zalloc(sizeof(*dt), KM_SLEEP);
419 dt->_cookie = pbm;
420 dt->_parent = pdt;
421 #define PCOPY(x) dt->x = pdt->x
422 dt->_dmamap_create = pyro_dmamap_create;
423 PCOPY(_dmamap_destroy);
424 dt->_dmamap_load = iommu_dvmamap_load;
425 PCOPY(_dmamap_load_mbuf);
426 PCOPY(_dmamap_load_uio);
427 dt->_dmamap_load_raw = iommu_dvmamap_load_raw;
428 dt->_dmamap_unload = iommu_dvmamap_unload;
429 dt->_dmamap_sync = iommu_dvmamap_sync;
430 dt->_dmamem_alloc = iommu_dvmamem_alloc;
431 dt->_dmamem_free = iommu_dvmamem_free;
432 dt->_dmamem_map = iommu_dvmamem_map;
433 dt->_dmamem_unmap = iommu_dvmamem_unmap;
434 PCOPY(_dmamem_mmap);
435 #undef PCOPY
436 return (dt);
437 }
438
439 pci_chipset_tag_t
pyro_alloc_chipset(struct pyro_pbm * pbm,int node,pci_chipset_tag_t pc)440 pyro_alloc_chipset(struct pyro_pbm *pbm, int node, pci_chipset_tag_t pc)
441 {
442 pci_chipset_tag_t npc;
443
444 npc = kmem_alloc(sizeof *npc, KM_SLEEP);
445 memcpy(npc, pc, sizeof *pc);
446 npc->cookie = pbm;
447 npc->rootnode = node;
448 npc->spc_conf_read = pyro_conf_read;
449 npc->spc_conf_write = pyro_conf_write;
450 npc->spc_intr_map = pyro_intr_map;
451 npc->spc_intr_establish = pyro_pci_intr_establish;
452 npc->spc_find_ino = NULL;
453 return (npc);
454 }
455
456 int
pyro_dmamap_create(bus_dma_tag_t t,bus_size_t size,int nsegments,bus_size_t maxsegsz,bus_size_t boundary,int flags,bus_dmamap_t * dmamp)457 pyro_dmamap_create(bus_dma_tag_t t, bus_size_t size,
458 int nsegments, bus_size_t maxsegsz, bus_size_t boundary, int flags,
459 bus_dmamap_t *dmamp)
460 {
461 struct pyro_pbm *pbm = t->_cookie;
462 int error;
463
464 error = bus_dmamap_create(t->_parent, size, nsegments, maxsegsz,
465 boundary, flags, dmamp);
466 if (error == 0)
467 (*dmamp)->_dm_cookie = &pbm->pp_sb;
468 return error;
469 }
470
471 int
pyro_bus_map(bus_space_tag_t t,bus_addr_t offset,bus_size_t size,int flags,vaddr_t unused,bus_space_handle_t * hp)472 pyro_bus_map(bus_space_tag_t t, bus_addr_t offset,
473 bus_size_t size, int flags, vaddr_t unused, bus_space_handle_t *hp)
474 {
475 struct pyro_pbm *pbm = t->cookie;
476 struct pyro_softc *sc = pbm->pp_sc;
477 int i, ss;
478
479 DPRINTF(PDB_BUSMAP, ("pyro_bus_map: type %d off %qx sz %qx flags %d",
480 t->type,
481 (unsigned long long)offset,
482 (unsigned long long)size,
483 flags));
484
485 /*
486 * BUS_SPACE_MAP_PREFETCHABLE causes hard hangs on schizo, so weed it
487 * out for now until someone can verify whether it works on pyro
488 */
489 flags &= ~BUS_SPACE_MAP_PREFETCHABLE;
490
491 ss = sparc_pci_childspace(t->type);
492 DPRINTF(PDB_BUSMAP, (" cspace %d", ss));
493
494 if (t->parent == 0 || t->parent->sparc_bus_map == 0) {
495 printf("\n_pyro_bus_map: invalid parent");
496 return (EINVAL);
497 }
498
499 for (i = 0; i < pbm->pp_nrange; i++) {
500 bus_addr_t paddr;
501 struct pyro_range *pr = &pbm->pp_range[i];
502
503 if (((pr->cspace >> 24) & 0x03) != ss)
504 continue;
505
506 paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset);
507 return ((*sc->sc_bustag->sparc_bus_map)(t, paddr, size,
508 flags, 0, hp));
509 }
510
511 return (EINVAL);
512 }
513
514 paddr_t
pyro_bus_mmap(bus_space_tag_t t,bus_addr_t paddr,off_t off,int prot,int flags)515 pyro_bus_mmap(bus_space_tag_t t, bus_addr_t paddr,
516 off_t off, int prot, int flags)
517 {
518 bus_addr_t offset = paddr;
519 struct pyro_pbm *pbm = t->cookie;
520 struct pyro_softc *sc = pbm->pp_sc;
521 int i, ss;
522
523 /*
524 * BUS_SPACE_MAP_PREFETCHABLE causes hard hangs on schizo, so weed it
525 * out for now until someone can verify whether it works on pyro
526 */
527 flags &= ~BUS_SPACE_MAP_PREFETCHABLE;
528
529 ss = sparc_pci_childspace(t->type);
530
531 DPRINTF(PDB_BUSMAP, ("pyro_bus_mmap: prot %d flags %d pa %qx\n",
532 prot, flags, (unsigned long long)paddr));
533
534 if (t->parent == 0 || t->parent->sparc_bus_mmap == 0) {
535 printf("\n_pyro_bus_mmap: invalid parent");
536 return (-1);
537 }
538
539 for (i = 0; i < pbm->pp_nrange; i++) {
540 struct pyro_range *pr = &pbm->pp_range[i];
541
542 if (((pr->cspace >> 24) & 0x03) != ss)
543 continue;
544
545 paddr = BUS_ADDR(pr->phys_hi, pr->phys_lo + offset);
546 return (bus_space_mmap(sc->sc_bustag, paddr, off,
547 prot, flags));
548 }
549
550 return (-1);
551 }
552
553 void *
pyro_intr_establish(bus_space_tag_t t,int ihandle,int level,int (* handler)(void *),void * arg,void (* fastvec)(void))554 pyro_intr_establish(bus_space_tag_t t, int ihandle, int level,
555 int (*handler)(void *), void *arg, void (*fastvec)(void) /* ignored */)
556 {
557 struct pyro_pbm *pbm = t->cookie;
558 struct pyro_softc *sc = pbm->pp_sc;
559 struct intrhand *ih = NULL;
560 volatile u_int64_t *intrmapptr = NULL, *intrclrptr = NULL;
561 u_int64_t *imapbase, *iclrbase;
562 int ino;
563
564 ino = INTINO(ihandle);
565 DPRINTF(PDB_INTR, ("%s: ih %lx; level %d ino %#x", __func__, (u_long)ihandle, level, ino));
566
567 if (level == IPL_NONE)
568 level = INTLEV(ihandle);
569 if (level == IPL_NONE) {
570 printf(": no IPL, setting IPL 2.\n");
571 level = 2;
572 }
573
574 imapbase = (uint64_t *)((uintptr_t)bus_space_vaddr(sc->sc_bustag, sc->sc_csrh) + 0x1000);
575 iclrbase = (uint64_t *)((uintptr_t)bus_space_vaddr(sc->sc_bustag, sc->sc_csrh) + 0x1400);
576 intrmapptr = &imapbase[ino];
577 intrclrptr = &iclrbase[ino];
578 DPRINTF(PDB_INTR, (" mapptr %p clrptr %p\n", intrmapptr, intrclrptr));
579
580 ino |= INTVEC(ihandle);
581
582 ih = intrhand_alloc();
583
584 /* Register the map and clear intr registers */
585 ih->ih_map = intrmapptr;
586 ih->ih_clr = intrclrptr;
587
588 ih->ih_ivec = ihandle;
589 ih->ih_fun = handler;
590 ih->ih_arg = arg;
591 ih->ih_pil = level;
592 ih->ih_number = ino;
593 ih->ih_pending = 0;
594
595 intr_establish(ih->ih_pil, level != IPL_VM, ih);
596
597 if (intrmapptr != NULL) {
598 u_int64_t imap;
599
600 imap = *intrmapptr;
601 DPRINTF(PDB_INTR, ("%s: read intrmap = %016qx", __func__,
602 (unsigned long long)imap));
603 imap &= ~FIRE_INTRMAP_INT_CNTRL_NUM_MASK;
604 imap |= FIRE_INTRMAP_INT_CNTRL_NUM0;
605 DPRINTF(PDB_INTR, ("; set intr group intrmap = %016qx",
606 (unsigned long long)imap));
607 if (sc->sc_oberon) {
608 imap &= ~OBERON_INTRMAP_T_DESTID_MASK;
609 imap |= CPU_JUPITERID <<
610 OBERON_INTRMAP_T_DESTID_SHIFT;
611 } else {
612 imap &= ~FIRE_INTRMAP_T_JPID_MASK;
613 imap |= CPU_UPAID << FIRE_INTRMAP_T_JPID_SHIFT;
614 }
615 DPRINTF(PDB_INTR, ("; set cpuid num intrmap = %016qx",
616 (unsigned long long)imap));
617 imap |= INTMAP_V;
618 *intrmapptr = imap;
619 DPRINTF(PDB_INTR, ("; writing intrmap = %016qx",
620 (unsigned long long)imap));
621 imap = *intrmapptr;
622 ih->ih_number |= imap & INTMAP_INR;
623 DPRINTF(PDB_INTR, ("; reread intrmap = %016qx, "
624 "set ih_number to %x\n",
625 (unsigned long long)imap, ih->ih_number));
626 }
627 if (intrclrptr) {
628 /* set state to IDLE */
629 *intrclrptr = 0;
630 }
631
632 return (ih);
633 }
634
635 static void *
pyro_pci_intr_establish(pci_chipset_tag_t pc,pci_intr_handle_t ih,int level,int (* func)(void *),void * arg)636 pyro_pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level,
637 int (*func)(void *), void *arg)
638 {
639 void *cookie;
640 struct pyro_pbm *pbm = (struct pyro_pbm *)pc->cookie;
641
642 DPRINTF(PDB_INTR, ("%s: ih %lx; level %d\n", __func__, (u_long)ih, level));
643 cookie = bus_intr_establish(pbm->pp_memt, ih, level, func, arg);
644
645 DPRINTF(PDB_INTR, ("%s: returning handle %p\n", __func__, cookie));
646 return (cookie);
647 }
648