1 /* $Id: pinctrl_prep.c,v 1.4 2013/10/07 17:36:40 matt Exp $ */
2
3 /*
4 * Copyright (c) 2012 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Petri Laakso.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include <sys/param.h>
33 #include <sys/cdefs.h>
34 #include <sys/types.h>
35
36 #include <arm/imx/imx23_pinctrlreg.h>
37
38 #include <lib/libsa/stand.h>
39
40 #include "common.h"
41
42 #define CTRL (HW_PINCTRL_BASE + HW_PINCTRL_CTRL)
43 #define CTRL_S (HW_PINCTRL_BASE + HW_PINCTRL_CTRL_SET)
44 #define CTRL_C (HW_PINCTRL_BASE + HW_PINCTRL_CTRL_CLR)
45 #define CTRL_MUX0 (HW_PINCTRL_BASE + HW_PINCTRL_MUXSEL0)
46 #define CTRL_MUX0_S (HW_PINCTRL_BASE + HW_PINCTRL_MUXSEL0_SET)
47 #define CTRL_MUX0_C (HW_PINCTRL_BASE + HW_PINCTRL_MUXSEL0_CLR)
48 #define CTRL_MUX1 (CTRL_MUX0 + 0x10)
49 #define CTRL_MUX1_S (CTRL_MUX0_S + 0x10)
50 #define CTRL_MUX1_C (CTRL_MUX0_C + 0x10)
51 #define CTRL_MUX2 (CTRL_MUX0 + 0x20)
52 #define CTRL_MUX2_S (CTRL_MUX0_S + 0x20)
53 #define CTRL_MUX2_C (CTRL_MUX0_C + 0x20)
54 #define CTRL_MUX3 (CTRL_MUX0 + 0x30)
55 #define CTRL_MUX3_S (CTRL_MUX0_S + 0x30)
56 #define CTRL_MUX3_C (CTRL_MUX0_C + 0x30)
57 #define CTRL_MUX4 (CTRL_MUX0 + 0x40)
58 #define CTRL_MUX4_S (CTRL_MUX0_S + 0x40)
59 #define CTRL_MUX4_C (CTRL_MUX0_C + 0x40)
60 #define CTRL_MUX5 (CTRL_MUX0 + 0x50)
61 #define CTRL_MUX5_S (CTRL_MUX0_S + 0x50)
62 #define CTRL_MUX5_C (CTRL_MUX0_C + 0x50)
63 #define CTRL_MUX6 (CTRL_MUX0 + 0x60)
64 #define CTRL_MUX6_S (CTRL_MUX0_S + 0x60)
65 #define CTRL_MUX6_C (CTRL_MUX0_C + 0x60)
66 #define CTRL_MUX7 (CTRL_MUX0 + 0x70)
67 #define CTRL_MUX7_S (CTRL_MUX0_S + 0x70)
68 #define CTRL_MUX7_C (CTRL_MUX0_C + 0x70)
69
70 #define CTRL_DRV0 (HW_PINCTRL_BASE + HW_PINCTRL_DRIVE0)
71 #define CTRL_DRV0_S (HW_PINCTRL_BASE + HW_PINCTRL_DRIVE0_SET)
72 #define CTRL_DRV0_C (HW_PINCTRL_BASE + HW_PINCTRL_DRIVE0_CLR)
73 #define CTRL_DRV8 (CTRL_DRV0 + 0x80)
74 #define CTRL_DRV8_S (CTRL_DRV0_S + 0x80)
75 #define CTRL_DRV8_C (CTRL_DRV0_C + 0x80)
76 #define CTRL_DRV9 (CTRL_DRV0 + 0x90)
77 #define CTRL_DRV9_S (CTRL_DRV0_S + 0x90)
78 #define CTRL_DRV9_C (CTRL_DRV0_C + 0x90)
79 #define CTRL_DRV10 (CTRL_DRV0 + 0xa0)
80 #define CTRL_DRV10_S (CTRL_DRV0_S + 0xa0)
81 #define CTRL_DRV10_C (CTRL_DRV0_C + 0xa0)
82 #define CTRL_DRV11 (CTRL_DRV0 + 0xb0)
83 #define CTRL_DRV11_S (CTRL_DRV0_S + 0xb0)
84 #define CTRL_DRV11_C (CTRL_DRV0_C + 0xb0)
85 #define CTRL_DRV12 (CTRL_DRV0 + 0xc0)
86 #define CTRL_DRV12_S (CTRL_DRV0_S + 0xc0)
87 #define CTRL_DRV12_C (CTRL_DRV0_C + 0xc0)
88 #define CTRL_DRV13 (CTRL_DRV0 + 0xd0)
89 #define CTRL_DRV13_S (CTRL_DRV0_S + 0xd0)
90 #define CTRL_DRV13_C (CTRL_DRV0_C + 0xd0)
91 #define CTRL_DRV14 (CTRL_DRV0 + 0xe0)
92 #define CTRL_DRV14_S (CTRL_DRV0_S + 0xe0)
93 #define CTRL_DRV14_C (CTRL_DRV0_C + 0xe0)
94
95 #define CTRL_PULL0 (HW_PINCTRL_BASE + HW_PINCTRL_PULL0)
96 #define CTRL_PULL1 (CTRL_PULL0 + 0x10)
97 #define CTRL_PULL2 (CTRL_PULL0 + 0x20)
98 #define CTRL_PULL3 (CTRL_PULL0 + 0x30)
99
100 /*
101 * Configure initial pin settings.
102 */
103 int
pinctrl_prep(void)104 pinctrl_prep(void)
105 {
106
107 REG_WR(CTRL_C, (HW_PINCTRL_CTRL_SFTRST | HW_PINCTRL_CTRL_CLKGATE));
108 delay(10000);
109
110 /*
111 * EMI MUX.
112 */
113 REG_WR(CTRL_MUX4_C, 0xfffc0000); /* A00:06 */
114 REG_WR(CTRL_MUX5_C, 0xfc3fffff); /* A07:12, BA0:1, CASN, CE0N,
115 * CE1N, CKE, RASN, WEN */
116 REG_WR(CTRL_MUX6_C, 0xffffffff); /* D00:15 */
117 REG_WR(CTRL_MUX7_C, 0xfff); /* DQM0:1, DQS0:1, CLK, CLKN */
118
119 /*
120 * EMI pin drive strength and voltage to 12mA @ 2.5V.
121 */
122 REG_WR(CTRL_DRV9, 0x22222220); /* A00:06 */
123 REG_WR(CTRL_DRV10, 0x22222222); /* A07:A12, BA0:1 */
124 REG_WR(CTRL_DRV11, 0x22200222); /* CASN, CE0N, CE1N, CKE, RASN, WEN */
125 REG_WR(CTRL_DRV12, 0x22222222); /* D00:07 */
126 REG_WR(CTRL_DRV13, 0x22222222); /* D08:15 */
127 REG_WR(CTRL_DRV14, 0x222222); /* DQM0:1, DQS0:1, CLK, CLKN */
128
129 /*
130 * Disable EMI pad keepers.
131 */
132 REG_WR(CTRL_PULL3, 0x3ffff); /* D00:D15, DQM0:1 */
133
134 /*
135 * SSP MUX.
136 */
137 REG_WR(CTRL_MUX4_C, 0x3ff3); /* CMD, DATA0:3, SCK */
138 REG_WR(CTRL_MUX4_S, 0xc); /* SSP1_DETECT as GPIO */
139
140 /*
141 * SSP pin drive strength.
142 */
143 REG_WR(CTRL_DRV8, 0x01111101); /* CMD, DATA0:3, SCK to 8mA
144 * SSP1_DETECT to 4mA */
145 /*
146 * SSP pull ups.
147 */
148 REG_WR(CTRL_PULL2, 0x3d); /* Pull-up DATA0:3, CMD and
149 * no pull-up SSP1_DETECT */
150 /*
151 * Debug UART MUX.
152 */
153 REG_WR(CTRL_MUX3_C, 0xf00000);
154 REG_WR(CTRL_MUX3_S, 0xa00000);
155
156 return 0;
157 }
158