xref: /netbsd-src/sys/arch/arm/pci/pci_smccc.c (revision 53a7ab421c95689922501594407bcbf263dca41f)
1 /* $NetBSD: pci_smccc.c,v 1.1 2021/08/07 21:23:37 jmcneill Exp $ */
2 
3 /*-
4  * Copyright (c) 2021 Jared McNeill <jmcneill@invisible.ca>
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: pci_smccc.c,v 1.1 2021/08/07 21:23:37 jmcneill Exp $");
31 
32 #include <sys/param.h>
33 #include <sys/kernel.h>
34 
35 #include <arm/arm/smccc.h>
36 #include <arm/pci/pci_smccc.h>
37 
38 /* Minimum SMCCC version required for PCI_VERSION call. */
39 #define	SMCCC_VERSION_1_1	0x10001
40 
41 /* PCI Configuration Space Access ABI functions */
42 #define	PCI_VERSION		0x84000130
43 #define	PCI_FEATURES		0x84000131
44 #define	PCI_READ		0x84000132
45 #define	PCI_WRITE		0x84000133
46 #define	PCI_GET_SEG_INFO	0x84000134
47 #define	 GET_SEG_INFO_BUS_START		__BITS(7,0)
48 #define	 GET_SEG_INFO_BUS_END		__BITS(15,8)
49 
50 static int
pci_smccc_call(uint32_t fid,register_t arg1,register_t arg2,register_t arg3,register_t arg4,register_t * res0,register_t * res1,register_t * res2,register_t * res3)51 pci_smccc_call(uint32_t fid,
52     register_t arg1, register_t arg2, register_t arg3, register_t arg4,
53     register_t *res0, register_t *res1, register_t *res2, register_t *res3)
54 {
55 	static int smccc_ver;
56 
57 	if (smccc_ver == 0) {
58 		smccc_ver = smccc_version();
59 	}
60 	if (smccc_ver < SMCCC_VERSION_1_1) {
61 		return SMCCC_NOT_SUPPORTED;
62 	}
63 
64 	return smccc_call(fid, arg1, arg2, arg3, arg4,
65 			  res0, res1, res2, res3);
66 }
67 
68 int
pci_smccc_version(void)69 pci_smccc_version(void)
70 {
71 	return pci_smccc_call(PCI_VERSION, 0, 0, 0, 0,
72 			      NULL, NULL, NULL, NULL);
73 }
74 
75 int
pci_smccc_features(uint32_t fid)76 pci_smccc_features(uint32_t fid)
77 {
78 	return pci_smccc_call(PCI_FEATURES, fid, 0, 0, 0,
79 			      NULL, NULL, NULL, NULL);
80 }
81 
82 int
pci_smccc_read(uint32_t sbdf,uint32_t offset,uint32_t access_size,uint32_t * data)83 pci_smccc_read(uint32_t sbdf, uint32_t offset, uint32_t access_size,
84     uint32_t *data)
85 {
86 	register_t value;
87 	int status;
88 
89 	status = pci_smccc_call(PCI_READ, sbdf, offset, access_size, 0,
90 				NULL, &value, NULL, NULL);
91 	if (status == SMCCC_SUCCESS) {
92 		*data = value;
93 	}
94 
95 	return status;
96 }
97 
98 int
pci_smccc_write(uint32_t sbdf,uint32_t offset,uint32_t access_size,uint32_t data)99 pci_smccc_write(uint32_t sbdf, uint32_t offset, uint32_t access_size,
100     uint32_t data)
101 {
102 	return pci_smccc_call(PCI_WRITE, sbdf, offset, access_size, data,
103 			      NULL, NULL, NULL, NULL);
104 }
105 
106 int
pci_smccc_get_seg_info(uint16_t seg,uint8_t * bus_start,uint8_t * bus_end,uint16_t * next_seg)107 pci_smccc_get_seg_info(uint16_t seg, uint8_t *bus_start, uint8_t *bus_end,
108     uint16_t *next_seg)
109 {
110 	register_t res1, res2;
111 	int status;
112 
113 	status = pci_smccc_call(PCI_GET_SEG_INFO, seg, 0, 0, 0,
114 				NULL, &res1, &res2, NULL);
115 	if (status == SMCCC_SUCCESS) {
116 		*bus_start = __SHIFTOUT(res1, GET_SEG_INFO_BUS_START);
117 		*bus_end = __SHIFTOUT(res1, GET_SEG_INFO_BUS_END);
118 		*next_seg = (uint16_t)res2;
119 	}
120 
121 	return status;
122 }
123