1 /* $NetBSD: pci_mace.c,v 1.26 2023/12/20 15:29:07 thorpej Exp $ */
2
3 /*
4 * Copyright (c) 2001,2003 Christopher Sekiya
5 * Copyright (c) 2000 Soren S. Jorvang
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed for the
19 * NetBSD Project. See http://www.NetBSD.org/ for
20 * information about NetBSD.
21 * 4. The name of the author may not be used to endorse or promote products
22 * derived from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 */
35
36 #include <sys/cdefs.h>
37 __KERNEL_RCSID(0, "$NetBSD: pci_mace.c,v 1.26 2023/12/20 15:29:07 thorpej Exp $");
38
39 #include "opt_pci.h"
40 #include "pci.h"
41
42 #include <sys/param.h>
43 #include <sys/device.h>
44 #include <sys/systm.h>
45
46 #include <machine/cpu.h>
47 #include <machine/locore.h>
48 #include <machine/autoconf.h>
49 #include <machine/vmparam.h>
50 #include <sys/bus.h>
51 #include <machine/machtype.h>
52
53 #include <mips/cache.h>
54
55 #include <dev/pci/pcivar.h>
56 #include <dev/pci/pcireg.h>
57 #include <dev/pci/pcidevs.h>
58
59 #include <dev/pci/pciconf.h>
60
61 #include <sgimips/mace/macereg.h>
62 #include <sgimips/mace/macevar.h>
63
64 #include <sgimips/mace/pcireg_mace.h>
65
66 #ifndef __mips_o32
67 #define USE_HIGH_PCI
68 #endif
69
70
71 struct macepci_softc {
72 struct sgimips_pci_chipset sc_pc;
73 };
74
75 static int macepci_match(device_t, cfdata_t, void *);
76 static void macepci_attach(device_t, device_t, void *);
77 static int macepci_bus_maxdevs(pci_chipset_tag_t, int);
78 static pcireg_t macepci_conf_read(pci_chipset_tag_t, pcitag_t, int);
79 static void macepci_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t);
80 static int macepci_intr_map(const struct pci_attach_args *,
81 pci_intr_handle_t *);
82 static const char *
83 macepci_intr_string(pci_chipset_tag_t, pci_intr_handle_t,
84 char *, size_t);
85 static int macepci_intr(void *);
86
87 CFATTACH_DECL_NEW(macepci, sizeof(struct macepci_softc),
88 macepci_match, macepci_attach, NULL, NULL);
89
90 static void pcimem_bus_mem_init(bus_space_tag_t, void *);
91 static void pciio_bus_mem_init(bus_space_tag_t, void *);
92 static struct mips_bus_space pcimem_mbst;
93 static struct mips_bus_space pciio_mbst;
94 bus_space_tag_t mace_pci_memt = NULL;
95 bus_space_tag_t mace_pci_iot = NULL;
96
97 #define PCI_IO_START 0x00001000
98 #define PCI_IO_END 0x01ffffff
99 #define PCI_IO_SIZE ((PCI_IO_END - PCI_IO_START) + 1)
100
101 #ifdef USE_HIGH_PCI
102 #define PCI_MEM_START 0x80000000
103 #define PCI_MEM_END 0xffffffff
104 #else /* ! USE_HIGH_PCI */
105 /* XXX no idea why we limit ourselves to only half of the 32MB window */
106 #define PCI_MEM_START 0x80100000
107 #define PCI_MEM_END 0x81ffffff
108 #endif /* USE_HIGH_PCI */
109
110 #define PCI_MEM_SIZE ((PCI_MEM_END - PCI_MEM_START) + 1)
111
112 static int
macepci_match(device_t parent,cfdata_t match,void * aux)113 macepci_match(device_t parent, cfdata_t match, void *aux)
114 {
115
116 return (1);
117 }
118
119 static void
macepci_attach(device_t parent,device_t self,void * aux)120 macepci_attach(device_t parent, device_t self, void *aux)
121 {
122 struct macepci_softc *sc = device_private(self);
123 pci_chipset_tag_t pc = &sc->sc_pc;
124 struct mace_attach_args *maa = aux;
125 struct pcibus_attach_args pba;
126 u_int32_t control;
127 int rev;
128
129 if (bus_space_subregion(maa->maa_st, maa->maa_sh,
130 maa->maa_offset, 0, &pc->ioh) )
131 panic("macepci_attach: couldn't map");
132
133 pc->iot = maa->maa_st;
134
135 rev = bus_space_read_4(pc->iot, pc->ioh, MACEPCI_REVISION);
136 printf(": rev %d\n", rev);
137
138 pcimem_bus_mem_init(&pcimem_mbst, NULL);
139 mace_pci_memt = &pcimem_mbst;
140 pciio_bus_mem_init(&pciio_mbst, NULL);
141 mace_pci_iot = &pciio_mbst;
142
143 pc->pc_bus_maxdevs = macepci_bus_maxdevs;
144 pc->pc_conf_read = macepci_conf_read;
145 pc->pc_conf_write = macepci_conf_write;
146 pc->pc_intr_map = macepci_intr_map;
147 pc->pc_intr_string = macepci_intr_string;
148 pc->intr_establish = mace_intr_establish;
149 pc->intr_disestablish = mace_intr_disestablish;
150
151 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_ERROR_ADDR, 0);
152 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_ERROR_FLAGS, 0);
153
154 /* Turn on PCI error interrupts */
155 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONTROL,
156 MACE_PCI_CONTROL_SERR_ENA |
157 MACE_PCI_CONTROL_PARITY_ERR |
158 MACE_PCI_CONTROL_PARK_LIU |
159 MACE_PCI_CONTROL_OVERRUN_INT |
160 MACE_PCI_CONTROL_PARITY_INT |
161 MACE_PCI_CONTROL_SERR_INT |
162 MACE_PCI_CONTROL_IT_INT |
163 MACE_PCI_CONTROL_RE_INT |
164 MACE_PCI_CONTROL_DPED_INT |
165 MACE_PCI_CONTROL_TAR_INT |
166 MACE_PCI_CONTROL_MAR_INT);
167
168 /*
169 * Enable all MACE PCI interrupts. They will be masked by
170 * the CRIME code.
171 */
172 control = bus_space_read_4(pc->iot, pc->ioh, MACEPCI_CONTROL);
173 control |= CONTROL_INT_MASK;
174 bus_space_write_4(pc->iot, pc->ioh, MACEPCI_CONTROL, control);
175
176 #if NPCI > 0
177 struct pciconf_resources *pcires = pciconf_resource_init();
178
179 pciconf_resource_add(pcires, PCICONF_RESOURCE_IO,
180 PCI_IO_START, PCI_IO_SIZE);
181 pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
182 PCI_MEM_START, PCI_MEM_SIZE);
183
184 pci_configure_bus(pc, pcires, 0,
185 mips_cache_info.mci_dcache_align);
186
187 pciconf_resource_fini(pcires);
188
189 memset(&pba, 0, sizeof pba);
190 pba.pba_iot = mace_pci_iot;
191 pba.pba_memt = mace_pci_memt;
192 pba.pba_dmat = &pci_bus_dma_tag;
193 pba.pba_dmat64 = NULL;
194 pba.pba_bus = 0;
195 pba.pba_bridgetag = NULL;
196 pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY |
197 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY;
198 pba.pba_pc = pc;
199
200 #ifdef MACEPCI_IO_WAS_BUGGY
201 if (rev == 0)
202 pba.pba_flags &= ~PCI_FLAGS_IO_OKAY; /* Buggy? */
203 #endif
204
205 cpu_intr_establish(maa->maa_intr, IPL_NONE, macepci_intr, sc);
206
207 config_found(self, &pba, pcibusprint, CFARGS_NONE);
208 #endif
209 }
210
211 int
macepci_bus_maxdevs(pci_chipset_tag_t pc,int busno)212 macepci_bus_maxdevs(pci_chipset_tag_t pc, int busno)
213 {
214
215 if (busno == 0)
216 return 5; /* 2 on-board SCSI chips, slots 0, 1 and 2 */
217 else
218 return 0; /* XXX */
219 }
220
221 pcireg_t
macepci_conf_read(pci_chipset_tag_t pc,pcitag_t tag,int reg)222 macepci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
223 {
224 pcireg_t data;
225
226 if ((unsigned int)reg >= PCI_CONF_SIZE)
227 return (pcireg_t) -1;
228
229 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_ADDR, (tag | reg));
230 data = bus_space_read_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_DATA);
231 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_ADDR, 0);
232
233 return data;
234 }
235
236 void
macepci_conf_write(pci_chipset_tag_t pc,pcitag_t tag,int reg,pcireg_t data)237 macepci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
238 {
239
240 if ((unsigned int)reg >= PCI_CONF_SIZE)
241 return;
242
243 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_ADDR, (tag | reg));
244 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_DATA, data);
245 bus_space_write_4(pc->iot, pc->ioh, MACE_PCI_CONFIG_ADDR, 0);
246 }
247
248 int
macepci_intr_map(const struct pci_attach_args * pa,pci_intr_handle_t * ihp)249 macepci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
250 {
251 pci_chipset_tag_t pc = pa->pa_pc;
252 pcitag_t intrtag = pa->pa_intrtag;
253 int pin = pa->pa_intrpin;
254 int bus, dev, func, start;
255
256 pci_decompose_tag(pc, intrtag, &bus, &dev, &func);
257
258 if (dev < 3 && pin != PCI_INTERRUPT_PIN_A)
259 panic("SCSI0 and SCSI1 must be hardwired!");
260
261 switch (pin) {
262 default:
263 case PCI_INTERRUPT_PIN_NONE:
264 return -1;
265
266 case PCI_INTERRUPT_PIN_A:
267 /*
268 * Each of SCSI{0,1}, & slots 0 - 2 has dedicated interrupt
269 * for pin A?
270 */
271 *ihp = dev + 7;
272 return 0;
273
274 case PCI_INTERRUPT_PIN_B:
275 start = 0;
276 break;
277 case PCI_INTERRUPT_PIN_C:
278 start = 1;
279 break;
280 case PCI_INTERRUPT_PIN_D:
281 start = 2;
282 break;
283 }
284
285 /* Pins B,C,D are mapped to PCI_SHARED0 - PCI_SHARED2 interrupts */
286 *ihp = 13 /* PCI_SHARED0 */ + (start + dev - 3) % 3;
287 return 0;
288 }
289
290 const char *
macepci_intr_string(pci_chipset_tag_t pc,pci_intr_handle_t ih,char * buf,size_t len)291 macepci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih, char *buf,
292 size_t len)
293 {
294 snprintf(buf, len, "crime interrupt %d", ih);
295 return buf;
296 }
297
298
299 /*
300 * Handle PCI error interrupts.
301 */
302 int
macepci_intr(void * arg)303 macepci_intr(void *arg)
304 {
305 struct macepci_softc *sc = (struct macepci_softc *)arg;
306 pci_chipset_tag_t pc = &sc->sc_pc;
307 uint32_t error, address;
308
309 error = bus_space_read_4(pc->iot, pc->ioh, MACE_PCI_ERROR_FLAGS);
310 address = bus_space_read_4(pc->iot, pc->ioh, MACE_PCI_ERROR_ADDR);
311 if (error & 0xffc00000) {
312 if (error & MACE_PERR_MASTER_ABORT) {
313 /*
314 * this seems to be a more-or-less normal error
315 * condition (e.g., "pcictl pci0 list" generates
316 * a _lot_ of these errors, so no message for now
317 * while I figure out if I missed a trick somewhere.
318 */
319 }
320
321 if (error & MACE_PERR_TARGET_ABORT) {
322 printf("mace: target abort at %x\n", address);
323 }
324
325 if (error & MACE_PERR_DATA_PARITY_ERR) {
326 printf("mace: parity error at %x\n", address);
327 }
328
329 if (error & MACE_PERR_RETRY_ERR) {
330 printf("mace: retry error at %x\n", address);
331 }
332
333 if (error & MACE_PERR_ILLEGAL_CMD) {
334 printf("mace: illegal command at %x\n", address);
335 }
336
337 if (error & MACE_PERR_SYSTEM_ERR) {
338 printf("mace: system error at %x\n", address);
339 }
340
341 if (error & MACE_PERR_INTERRUPT_TEST) {
342 printf("mace: interrupt test at %x\n", address);
343 }
344
345 if (error & MACE_PERR_PARITY_ERR) {
346 printf("mace: parity error at %x\n", address);
347 }
348
349 if (error & MACE_PERR_RSVD) {
350 printf("mace: reserved condition at %x\n", address);
351 }
352
353 if (error & MACE_PERR_OVERRUN) {
354 printf("mace: overrun at %x\n", address);
355 }
356
357 /* clear all */
358 bus_space_write_4(pc->iot, pc->ioh,
359 MACE_PCI_ERROR_FLAGS, error & ~0xffc00000);
360 }
361 return 0;
362 }
363
364 /*
365 * use the 32MB windows to access PCI space when running a 32bit kernel,
366 * use full views at >4GB in LP64
367 * XXX access to PCI space is endian-twiddled which can't be turned off so we
368 * need to instruct bus_space to un-twiddle them for us so 8bit and 16bit
369 * accesses look little-endian
370 */
371 #define CHIP pcimem
372 #define CHIP_MEM /* defined */
373 #define CHIP_WRONG_ENDIAN
374
375 /*
376 * the lower 2GB of PCI space are two views of system memory, with and without
377 * endianness twiddling
378 */
379 #define CHIP_W1_BUS_START(v) 0x80000000UL
380 #define CHIP_W1_BUS_END(v) 0xffffffffUL
381 #ifdef USE_HIGH_PCI
382 #define CHIP_W1_SYS_START(v) MACE_PCI_HI_MEMORY
383 #define CHIP_W1_SYS_END(v) MACE_PCI_HI_MEMORY + 0x7fffffffUL
384 #else
385 #define CHIP_W1_SYS_START(v) MACE_PCI_LOW_MEMORY
386 #define CHIP_W1_SYS_END(v) MACE_PCI_LOW_MEMORY + 0x01ffffffUL
387 #endif
388
389 #include <mips/mips/bus_space_alignstride_chipdep.c>
390
391 #undef CHIP
392 #undef CHIP_W1_BUS_START
393 #undef CHIP_W1_BUS_END
394 #undef CHIP_W1_SYS_START
395 #undef CHIP_W1_SYS_END
396
397 #define CHIP pciio
398 /*
399 * Even though it's PCI IO space, it's memory mapped so there is no reason not
400 * to allow linear mappings or mmapings into userland. In fact we may need to
401 * do just that in order to use things like PCI graphics cards in X.
402 */
403 #define CHIP_MEM /* defined */
404 #define CHIP_W1_BUS_START(v) 0x00000000UL
405 #define CHIP_W1_BUS_END(v) 0xffffffffUL
406 #ifdef USE_HIGH_PCI
407 #define CHIP_W1_SYS_START(v) MACE_PCI_HI_IO
408 #define CHIP_W1_SYS_END(v) MACE_PCI_HI_IO + 0xffffffffUL
409 #else
410 #define CHIP_W1_SYS_START(v) MACE_PCI_LOW_IO
411 #define CHIP_W1_SYS_END(v) MACE_PCI_LOW_IO + 0x01ffffffUL
412 #endif
413
414 #include <mips/mips/bus_space_alignstride_chipdep.c>
415