1 /* $NetBSD: pci_gio.c,v 1.20 2023/12/20 15:29:07 thorpej Exp $ */
2
3 /*
4 * Copyright (c) 2006 Stephen M. Rumble
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __KERNEL_RCSID(0, "$NetBSD: pci_gio.c,v 1.20 2023/12/20 15:29:07 thorpej Exp $");
29
30 /*
31 * Glue for PCI devices that are connected to the GIO bus by various little
32 * GIO<->PCI ASICs.
33 *
34 * We presently support the following boards:
35 * o Phobos G100/G130/G160 (if_tlp, lxtphy)
36 * o Set Engineering GFE (if_tl, nsphy)
37 */
38
39 #include "opt_pci.h"
40 #include "pci.h"
41
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/device.h>
45
46 #include <sys/bus.h>
47 #include <machine/machtype.h>
48
49 #include <sgimips/gio/giovar.h>
50 #include <sgimips/gio/gioreg.h>
51 #include <sgimips/gio/giodevs.h>
52
53 #include <sgimips/dev/imcvar.h>
54
55 #include <mips/cache.h>
56
57 #include <dev/pci/pcivar.h>
58 #include <dev/pci/pcireg.h>
59 #include <dev/pci/pcidevs.h>
60 #include <dev/pci/pciconf.h>
61
62 int giopci_debug = 0;
63 #define DPRINTF(_x) if (giopci_debug) printf _x
64
65 struct giopci_softc {
66 struct sgimips_pci_chipset sc_pc;
67 int sc_slot;
68 int sc_gprid;
69 uint32_t sc_pci_len;
70 bus_space_tag_t sc_iot;
71 bus_space_handle_t sc_ioh;
72 };
73
74 static int giopci_match(device_t, cfdata_t, void *);
75 static void giopci_attach(device_t, device_t, void *);
76 static int giopci_bus_maxdevs(pci_chipset_tag_t, int);
77 static pcireg_t giopci_conf_read(pci_chipset_tag_t, pcitag_t, int);
78 static void giopci_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t);
79 static int giopci_conf_hook(pci_chipset_tag_t, int, int, int, pcireg_t);
80 static int giopci_intr_map(const struct pci_attach_args *,
81 pci_intr_handle_t *);
82 static const char *
83 giopci_intr_string(pci_chipset_tag_t, pci_intr_handle_t,
84 char *, size_t);
85 static void *giopci_intr_establish(int, int, int (*)(void *), void *);
86 static void giopci_intr_disestablish(void *);
87
88 #define PHOBOS_PCI_OFFSET 0x00100000
89 #define PHOBOS_PCI_LENGTH 128 /* ~arbitrary */
90 #define PHOBOS_TULIP_START 0x00101000
91 #define PHOBOS_TULIP_END 0x001fffff
92
93 #define SETENG_MAGIC_OFFSET 0x00020000
94 #define SETENG_MAGIC_VALUE 0x00001000
95 #define SETENG_PCI_OFFSET 0x00080000
96 #define SETENG_PCI_LENGTH 128 /* ~arbitrary */
97 #define SETENG_TLAN_START 0x00100000
98 #define SETENG_TLAN_END 0x001fffff
99
100 CFATTACH_DECL_NEW(giopci, sizeof(struct giopci_softc),
101 giopci_match, giopci_attach, NULL, NULL);
102
103 static void pcimem_bus_mem_init(bus_space_tag_t, void *);
104 static struct mips_bus_space pcimem_mbst;
105 bus_space_tag_t gio_pci_memt = NULL;
106
107 static int
giopci_match(device_t parent,cfdata_t match,void * aux)108 giopci_match(device_t parent, cfdata_t match, void *aux)
109 {
110 struct gio_attach_args *ga = aux;
111 int gprid;
112
113 /*
114 * I think that these cards are all GIO32-bis or GIO64. Thus
115 * they work in either Indigo2/Challenge M or
116 * Indy/Challenge S/Indigo R4k, according to form factor. However,
117 * there are some exceptions (e.g. my Indigo R4k won't power
118 * on with the Set Engineering card installed).
119 */
120 if (mach_type != MACH_SGI_IP20 && mach_type != MACH_SGI_IP22)
121 return (0);
122
123 gprid = GIO_PRODUCT_PRODUCTID(ga->ga_product);
124 if (gprid == PHOBOS_G100 || gprid == PHOBOS_G130 ||
125 gprid == PHOBOS_G160 || gprid == SETENG_GFE)
126 return (1);
127
128 return (0);
129 }
130
131 static void
giopci_attach(device_t parent,device_t self,void * aux)132 giopci_attach(device_t parent, device_t self, void *aux)
133 {
134 struct giopci_softc *sc = device_private(self);
135 pci_chipset_tag_t pc = &sc->sc_pc;
136 struct gio_attach_args *ga = aux;
137 uint32_t pci_off, pci_len, arb;
138 struct pcibus_attach_args pba;
139 u_long m_start, m_end;
140 #ifdef PCI_NETBSD_CONFIGURE
141 extern int pci_conf_debug;
142
143 pci_conf_debug = giopci_debug;
144 #endif
145
146 sc->sc_iot = ga->ga_iot;
147 sc->sc_slot = ga->ga_slot;
148 sc->sc_gprid = GIO_PRODUCT_PRODUCTID(ga->ga_product);
149
150 pcimem_bus_mem_init(&pcimem_mbst, NULL);
151 gio_pci_memt = &pcimem_mbst;
152
153 if (mach_type == MACH_SGI_IP22 &&
154 mach_subtype == MACH_SGI_IP22_FULLHOUSE)
155 arb = GIO_ARB_RT | GIO_ARB_MST | GIO_ARB_PIPE;
156 else
157 arb = GIO_ARB_RT | GIO_ARB_MST;
158
159 if (gio_arb_config(ga->ga_slot, arb)) {
160 printf(": failed to configure GIO bus arbiter\n");
161 return;
162 }
163
164 #if (NIMC > 0)
165 imc_disable_sysad_parity();
166 #endif
167
168 switch (sc->sc_gprid) {
169 case PHOBOS_G100:
170 case PHOBOS_G130:
171 case PHOBOS_G160:
172 pci_off = PHOBOS_PCI_OFFSET;
173 pci_len = PHOBOS_PCI_LENGTH;
174 m_start = MIPS_KSEG1_TO_PHYS(ga->ga_addr + PHOBOS_TULIP_START);
175 m_end = MIPS_KSEG1_TO_PHYS(ga->ga_addr + PHOBOS_TULIP_END);
176 break;
177
178 case SETENG_GFE:
179 /*
180 * NB: The SetEng board does not allow the ThunderLAN's DMA
181 * engine to properly transfer segments that span page
182 * boundaries. See sgimips/autoconf.c where we catch a
183 * tl(4) device attachment and create an appropriate
184 * proplib entry to enable the workaround.
185 */
186 pci_off = SETENG_PCI_OFFSET;
187 pci_len = SETENG_PCI_LENGTH;
188 m_start = MIPS_KSEG1_TO_PHYS(ga->ga_addr + SETENG_TLAN_START);
189 m_end = MIPS_KSEG1_TO_PHYS(ga->ga_addr + SETENG_TLAN_END);
190 bus_space_write_4(ga->ga_iot, ga->ga_ioh,
191 SETENG_MAGIC_OFFSET, SETENG_MAGIC_VALUE);
192 break;
193
194 default:
195 panic("giopci_attach: unsupported GIO product id 0x%02x",
196 sc->sc_gprid);
197 }
198
199 if (bus_space_subregion(ga->ga_iot, ga->ga_ioh, pci_off, pci_len,
200 &sc->sc_ioh)) {
201 printf("%s: unable to map PCI registers\n", device_xname(self));
202 return;
203 }
204 sc->sc_pci_len = pci_len;
205
206 pc->pc_bus_maxdevs = giopci_bus_maxdevs;
207 pc->pc_conf_read = giopci_conf_read;
208 pc->pc_conf_write = giopci_conf_write;
209 pc->pc_conf_hook = giopci_conf_hook;
210 pc->pc_intr_map = giopci_intr_map;
211 pc->pc_intr_string = giopci_intr_string;
212 pc->intr_establish = giopci_intr_establish;
213 pc->intr_disestablish = giopci_intr_disestablish;
214 pc->iot = ga->ga_iot;
215 pc->ioh = ga->ga_ioh;
216 pc->cookie = sc;
217
218 printf(": %s\n", gio_product_string(sc->sc_gprid));
219
220 #ifdef PCI_NETBSD_CONFIGURE
221 struct pciconf_resources *pcires = pciconf_resource_init();
222
223 pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM,
224 m_start, (m_end - m_start) + 1);
225
226 pci_configure_bus(pc, pcires, 0,
227 mips_cache_info.mci_dcache_align);
228
229 pciconf_resource_fini(pcires);
230 #endif
231
232 memset(&pba, 0, sizeof(pba));
233 pba.pba_memt = gio_pci_memt;
234 pba.pba_dmat = ga->ga_dmat;
235 pba.pba_pc = pc;
236 pba.pba_flags = PCI_FLAGS_MEM_OKAY;
237 /* NB: do not set PCI_FLAGS_{MRL,MRM,MWI}_OKAY -- true ?! */
238
239 config_found(self, &pba, pcibusprint, CFARGS_NONE);
240 }
241
242 static int
giopci_bus_maxdevs(pci_chipset_tag_t pc,int busno)243 giopci_bus_maxdevs(pci_chipset_tag_t pc, int busno)
244 {
245
246 return (busno == 0);
247 }
248
249 static pcireg_t
giopci_conf_read(pci_chipset_tag_t pc,pcitag_t tag,int reg)250 giopci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
251 {
252 struct giopci_softc *sc = pc->cookie;
253 int bus, dev, func;
254 pcireg_t data;
255
256 if ((unsigned int)reg >= PCI_CONF_SIZE)
257 return (pcireg_t) -1;
258
259 pci_decompose_tag(pc, tag, &bus, &dev, &func);
260 if (bus != 0 || dev != 0 || func != 0)
261 return (0);
262
263 /* XXX - should just use bus_space_peek */
264 if (reg >= sc->sc_pci_len) {
265 DPRINTF(("giopci_conf_read: reg 0x%x out of bounds\n", reg));
266 return (0);
267 }
268
269 DPRINTF(("giopci_conf_read: reg 0x%x = 0x", reg));
270 data = bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg);
271 DPRINTF(("%08x\n", data));
272
273 return (data);
274 }
275
276 static void
giopci_conf_write(pci_chipset_tag_t pc,pcitag_t tag,int reg,pcireg_t data)277 giopci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
278 {
279 struct giopci_softc *sc = pc->cookie;
280 int bus, dev, func;
281
282 if ((unsigned int)reg >= PCI_CONF_SIZE)
283 return;
284
285 pci_decompose_tag(pc, tag, &bus, &dev, &func);
286 if (bus != 0 || dev != 0 || func != 0)
287 return;
288
289 /* XXX - should just use bus_space_poke */
290 if (reg >= sc->sc_pci_len) {
291 DPRINTF(("giopci_conf_write: reg 0x%x out of bounds "
292 "(val = 0x%08x)\n", reg, data));
293 return;
294 }
295
296 DPRINTF(("giopci_conf_write: reg 0x%x = 0x%08x\n", reg, data));
297 bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, data);
298 }
299
300 static int
giopci_conf_hook(pci_chipset_tag_t pc,int bus,int device,int function,pcireg_t id)301 giopci_conf_hook(pci_chipset_tag_t pc, int bus, int device, int function,
302 pcireg_t id)
303 {
304
305 /* All devices use memory accesses only. */
306 return (PCI_CONF_MAP_MEM | PCI_CONF_ENABLE_MEM | PCI_CONF_ENABLE_BM);
307 }
308
309 static int
giopci_intr_map(const struct pci_attach_args * pa,pci_intr_handle_t * ihp)310 giopci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
311 {
312 struct giopci_softc *sc = pa->pa_pc->cookie;
313
314 *ihp = sc->sc_slot;
315
316 return (0);
317 }
318
319 static const char *
giopci_intr_string(pci_chipset_tag_t pc,pci_intr_handle_t ih,char * buf,size_t len)320 giopci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih, char * buf,
321 size_t len)
322 {
323 snprintf(buf, len, "slot %s", (ih == GIO_SLOT_EXP0) ? "EXP0" :
324 (ih == GIO_SLOT_EXP1) ? "EXP1" : "GFX");
325 return buf;
326 }
327
328 static void *
giopci_intr_establish(int slot,int level,int (* func)(void *),void * arg)329 giopci_intr_establish(int slot, int level, int (*func)(void *), void *arg)
330 {
331
332 return (gio_intr_establish(slot, level, func, arg));
333 }
334
335 static void
giopci_intr_disestablish(void * cookie)336 giopci_intr_disestablish(void *cookie)
337 {
338
339 panic("giopci_intr_disestablish: impossible.");
340 }
341
342 #define CHIP pcimem
343 #define CHIP_MEM /* defined */
344 #define CHIP_WRONG_ENDIAN
345
346 #define CHIP_W1_BUS_START(v) 0x00000000UL
347 #define CHIP_W1_BUS_END(v) 0xffffffffUL
348 #define CHIP_W1_SYS_START(v) 0x00000000UL
349 #define CHIP_W1_SYS_END(v) 0xffffffffUL
350
351 #include <mips/mips/bus_space_alignstride_chipdep.c>
352