xref: /plan9/sys/src/cmd/aux/vga/pci.h (revision 9a747e4fd48b9f4522c70c07e8f882a15030f964)
1 enum {
2 	BusCBUS		= 0,		/* Corollary CBUS */
3 	BusCBUSII,			/* Corollary CBUS II */
4 	BusEISA,			/* Extended ISA */
5 	BusFUTURE,			/* IEEE Futurebus */
6 	BusINTERN,			/* Internal bus */
7 	BusISA,				/* Industry Standard Architecture */
8 	BusMBI,				/* Multibus I */
9 	BusMBII,			/* Multibus II */
10 	BusMCA,				/* Micro Channel Architecture */
11 	BusMPI,				/* MPI */
12 	BusMPSA,			/* MPSA */
13 	BusNUBUS,			/* Apple Macintosh NuBus */
14 	BusPCI,				/* Peripheral Component Interconnect */
15 	BusPCMCIA,			/* PC Memory Card International Association */
16 	BusTC,				/* DEC TurboChannel */
17 	BusVL,				/* VESA Local bus */
18 	BusVME,				/* VMEbus */
19 	BusXPRESS,			/* Express System Bus */
20 };
21 
22 #define MKBUS(t,b,d,f)	(((t)<<24)|(((b)&0xFF)<<16)|(((d)&0x1F)<<11)|(((f)&0x07)<<8))
23 #define BUSFNO(tbdf)	(((tbdf)>>8)&0x07)
24 #define BUSDNO(tbdf)	(((tbdf)>>11)&0x1F)
25 #define BUSBNO(tbdf)	(((tbdf)>>16)&0xFF)
26 #define BUSTYPE(tbdf)	((tbdf)>>24)
27 #define BUSBDF(tbdf)	((tbdf)&0x00FFFF00)
28 #define BUSUNKNOWN	(-1)
29 
30 /*
31  * PCI support code.
32  */
33 enum {					/* type 0 and type 1 pre-defined header */
34 	PciVID		= 0x00,		/* vendor ID */
35 	PciDID		= 0x02,		/* device ID */
36 	PciPCR		= 0x04,		/* command */
37 	PciPSR		= 0x06,		/* status */
38 	PciRID		= 0x08,		/* revision ID */
39 	PciCCRp		= 0x09,		/* programming interface class code */
40 	PciCCRu		= 0x0A,		/* sub-class code */
41 	PciCCRb		= 0x0B,		/* base class code */
42 	PciCLS		= 0x0C,		/* cache line size */
43 	PciLTR		= 0x0D,		/* latency timer */
44 	PciHDT		= 0x0E,		/* header type */
45 	PciBST		= 0x0F,		/* BIST */
46 
47 	PciBAR0		= 0x10,		/* base address */
48 	PciBAR1		= 0x14,
49 
50 	PciINTL		= 0x3C,		/* interrupt line */
51 	PciINTP		= 0x3D,		/* interrupt pin */
52 };
53 
54 enum {					/* type 0 pre-defined header */
55 	PciBAR2		= 0x18,
56 	PciBAR3		= 0x1C,
57 	PciBAR4		= 0x20,
58 	PciBAR5		= 0x24,
59 	PciCIS		= 0x28,		/* cardbus CIS pointer */
60 	PciSVID		= 0x2C,		/* subsystem vendor ID */
61 	PciSID		= 0x2E,		/* cardbus CIS pointer */
62 	PciEBAR0	= 0x30,		/* expansion ROM base address */
63 	PciMGNT		= 0x3E,		/* burst period length */
64 	PciMLT		= 0x3F,		/* maximum latency between bursts */
65 };
66 
67 enum {					/* type 1 pre-defined header */
68 	PciPBN		= 0x18,		/* primary bus number */
69 	PciSBN		= 0x19,		/* secondary bus number */
70 	PciUBN		= 0x1A,		/* subordinate bus number */
71 	PciSLTR		= 0x1B,		/* secondary latency timer */
72 	PciIBR		= 0x1C,		/* I/O base */
73 	PciILR		= 0x1D,		/* I/O limit */
74 	PciSPSR		= 0x1E,		/* secondary status */
75 	PciMBR		= 0x20,		/* memory base */
76 	PciMLR		= 0x22,		/* memory limit */
77 	PciPMBR		= 0x24,		/* prefetchable memory base */
78 	PciPMLR		= 0x26,		/* prefetchable memory limit */
79 	PciPUBR		= 0x28,		/* prefetchable base upper 32 bits */
80 	PciPULR		= 0x2C,		/* prefetchable limit upper 32 bits */
81 	PciIUBR		= 0x30,		/* I/O base upper 16 bits */
82 	PciIULR		= 0x32,		/* I/O limit upper 16 bits */
83 	PciEBAR1	= 0x28,		/* expansion ROM base address */
84 	PciBCR		= 0x3E,		/* bridge control register */
85 };
86 
87 typedef struct Pcidev Pcidev;
88 typedef struct Pcidev {
89 	int	tbdf;			/* type+bus+device+function */
90 	ushort	vid;			/* vendor ID */
91 	ushort	did;			/* device ID */
92 	uchar	rid;			/* revision ID */
93 
94 	struct {
95 		ulong	bar;		/* base address */
96 		int	size;
97 	} mem[6];
98 
99 	uchar	intl;			/* interrupt line */
100 	ushort	ccru;
101 
102 
103 	Pcidev*	list;
104 	Pcidev*	bridge;			/* down a bus */
105 	Pcidev*	link;			/* next device on this bno */
106 };
107