1 /* $NetBSD: orion.c,v 1.7 2021/08/30 00:04:30 rin Exp $ */
2 /*
3 * Copyright (c) 2010 KIYOHARA Takashi
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 __KERNEL_RCSID(0, "$NetBSD: orion.c,v 1.7 2021/08/30 00:04:30 rin Exp $");
30
31 #define _INTR_PRIVATE
32
33 #include "mvsocgpp.h"
34
35 #include <sys/param.h>
36 #include <sys/bus.h>
37
38 #include <machine/intr.h>
39
40 #include <arm/pic/picvar.h>
41 #include <arm/pic/picvar.h>
42
43 #include <arm/marvell/mvsocreg.h>
44 #include <arm/marvell/mvsocvar.h>
45 #include <arm/marvell/orionreg.h>
46
47 #include <dev/marvell/marvellreg.h>
48
49
50 static void orion_intr_init(void);
51
52 static void orion_pic_unblock_irqs(struct pic_softc *, size_t, uint32_t);
53 static void orion_pic_block_irqs(struct pic_softc *, size_t, uint32_t);
54 static void orion_pic_establish_irq(struct pic_softc *, struct intrsource *);
55 static void orion_pic_source_name(struct pic_softc *, int, char *, size_t);
56
57 static int orion_find_pending_irqs(void);
58
59 static void orion_getclks(vaddr_t);
60
61 static const char * const sources[64] = {
62 "Bridge(0)", "Host2CPU DB(1)", "CPU2Host DB(2)", "UART0(3)",
63 "UART1(4)", "TWSI(5)", "GPIO7_0(6)", "GPIO15_8(7)",
64 "GPIO23_16(8)", "GPIO31_24(9)", "PEX0Err(10)", "PEX0INT(11)",
65 "PEX1Err/USBCnt1", "PEX1INT(13)", "DEVErr(14)", "PCIErr(15)",
66 "USBBr(16)", "USBCnt0(17)", "GbERx(18)", "GbETx(19)",
67 "GbEMisc(20)", "GbESum(21)", "GbEErr(22)", "DMAErr(23)",
68 "IDMA0(24)", "IDMA1(25)", "IDMA2(26)", "IDMA3(27)",
69 "SecIntr(28)", "SataIntr(29)", "XOR0(30)", "XOR1(31)"
70 };
71
72 static struct pic_ops orion_picops = {
73 .pic_unblock_irqs = orion_pic_unblock_irqs,
74 .pic_block_irqs = orion_pic_block_irqs,
75 .pic_establish_irq = orion_pic_establish_irq,
76 .pic_source_name = orion_pic_source_name,
77 };
78 static struct pic_softc orion_pic = {
79 .pic_ops = &orion_picops,
80 .pic_maxsources = 32,
81 .pic_name = "orion_pic",
82 };
83
84
85 /*
86 * orion_bootstrap:
87 *
88 * Initialize the rest of the Orion dependences, making it
89 * ready to handle interrupts from devices.
90 */
91 void
orion_bootstrap(vaddr_t iobase)92 orion_bootstrap(vaddr_t iobase)
93 {
94
95 /* disable all interrupts */
96 write_mlmbreg(ORION_MLMB_MIRQIMR, 0);
97
98 /* disable all bridge interrupts */
99 write_mlmbreg(MVSOC_MLMB_MLMBIMR, 0);
100
101 mvsoc_intr_init = orion_intr_init;
102
103 #if NMVSOCGPP > 0
104 gpp_npins = 32;
105 gpp_irqbase = 64; /* Main(32) + Bridge(32) */
106 #endif
107
108 orion_getclks(iobase);
109 }
110
111 static void
orion_intr_init(void)112 orion_intr_init(void)
113 {
114 extern struct pic_softc mvsoc_bridge_pic;
115 void *ih __diagused;
116
117 pic_add(&orion_pic, 0);
118
119 pic_add(&mvsoc_bridge_pic, 32);
120 ih = intr_establish(ORION_IRQ_BRIDGE, IPL_HIGH, IST_LEVEL_HIGH,
121 pic_handle_intr, &mvsoc_bridge_pic);
122 KASSERT(ih != NULL);
123
124 find_pending_irqs = orion_find_pending_irqs;
125 }
126
127 /* ARGSUSED */
128 static void
orion_pic_unblock_irqs(struct pic_softc * pic,size_t irqbase,uint32_t irq_mask)129 orion_pic_unblock_irqs(struct pic_softc *pic, size_t irqbase, uint32_t irq_mask)
130 {
131
132 write_mlmbreg(ORION_MLMB_MIRQIMR,
133 read_mlmbreg(ORION_MLMB_MIRQIMR) | irq_mask);
134 }
135
136 /* ARGSUSED */
137 static void
orion_pic_block_irqs(struct pic_softc * pic,size_t irqbase,uint32_t irq_mask)138 orion_pic_block_irqs(struct pic_softc *pic, size_t irqbase, uint32_t irq_mask)
139 {
140
141 write_mlmbreg(ORION_MLMB_MIRQIMR,
142 read_mlmbreg(ORION_MLMB_MIRQIMR) & ~irq_mask);
143 }
144
145 /* ARGSUSED */
146 static void
orion_pic_establish_irq(struct pic_softc * pic,struct intrsource * is)147 orion_pic_establish_irq(struct pic_softc *pic, struct intrsource *is)
148 {
149 /* Nothing */
150 }
151
152 static void
orion_pic_source_name(struct pic_softc * pic,int irq,char * buf,size_t len)153 orion_pic_source_name(struct pic_softc *pic, int irq, char *buf, size_t len)
154 {
155
156 strlcpy(buf, sources[pic->pic_irqbase + irq], len);
157 }
158
159 /*
160 * Called with interrupts disabled
161 */
162 static int
orion_find_pending_irqs(void)163 orion_find_pending_irqs(void)
164 {
165 uint32_t pending;
166
167 pending =
168 read_mlmbreg(ORION_MLMB_MICR) & read_mlmbreg(ORION_MLMB_MIRQIMR);
169 if (pending == 0)
170 return 0;
171
172 return pic_mark_pending_sources(&orion_pic, 0, pending);
173 }
174
175 /*
176 * Clock functions
177 */
178
179 static void
orion_getclks(vaddr_t iobase)180 orion_getclks(vaddr_t iobase)
181 {
182 static const struct {
183 int armddrclkval;
184 uint32_t pclk;
185 uint32_t sysclk;
186 } sysclktbl[] = {
187 { ORION_PMISMPL_ARMDDRCLK_333_167, 333000000, 166666667 },
188 { ORION_PMISMPL_ARMDDRCLK_400_200, 400000000, 200000000 },
189 { ORION_PMISMPL_ARMDDRCLK_400_133, 400000000, 133333334 },
190 { ORION_PMISMPL_ARMDDRCLK_500_167, 500000000, 166666667 },
191 { ORION_PMISMPL_ARMDDRCLK_533_133, 533000000, 133333334 },
192 { ORION_PMISMPL_ARMDDRCLK_600_200, 600000000, 200000000 },
193 { ORION_PMISMPL_ARMDDRCLK_667_167, 667000000, 166666667 },
194 { ORION_PMISMPL_ARMDDRCLK_800_200, 800000000, 200000000 },
195 { ORION_PMISMPL_ARMDDRCLK_480_160, 480000000, 160000000 },
196 { ORION_PMISMPL_ARMDDRCLK_550_183, 550000000, 183333334 },
197 { ORION_PMISMPL_ARMDDRCLK_525_175, 525000000, 175000000 },
198 { ORION_PMISMPL_ARMDDRCLK_466_233, 466000000, 233000000 },
199 { ORION_PMISMPL_ARMDDRCLK_500_250, 500000000, 250000000 },
200 { ORION_PMISMPL_ARMDDRCLK_533_266, 533000000, 266000000 },
201 { ORION_PMISMPL_ARMDDRCLK_600_300, 600000000, 300000000 },
202 { ORION_PMISMPL_ARMDDRCLK_450_150, 450000000, 150000000 },
203 { ORION_PMISMPL_ARMDDRCLK_533_178, 533000000, 178000000 },
204 { ORION_PMISMPL_ARMDDRCLK_575_192, 575000000, 192000000 },
205 { ORION_PMISMPL_ARMDDRCLK_700_175, 700000000, 175000000 },
206 { ORION_PMISMPL_ARMDDRCLK_733_183, 733000000, 183333334 },
207 { ORION_PMISMPL_ARMDDRCLK_750_187, 750000000, 187000000 },
208 { ORION_PMISMPL_ARMDDRCLK_775_194, 775000000, 194000000 },
209 { ORION_PMISMPL_ARMDDRCLK_500_125, 500000000, 125000000 },
210 { ORION_PMISMPL_ARMDDRCLK_500_100, 500000000, 100000000 },
211 { ORION_PMISMPL_ARMDDRCLK_600_150, 600000000, 150000000 },
212 };
213 uint32_t reg, armddrclk, tclk;
214 uint16_t model;
215 int armddrclk_shift, tclk_shift, i;
216
217 model = mvsoc_model();
218 if (model == MARVELL_ORION_1_88F1181 ||
219 model == MARVELL_ORION_2_88F1281) {
220 armddrclk_shift = 6;
221 tclk_shift = 10;
222 } else {
223 armddrclk_shift = 4;
224 tclk_shift = 8;
225 }
226
227 reg = le32toh(*(volatile uint32_t *)(iobase + ORION_PMI_BASE +
228 ORION_PMI_SAMPLE_AT_RESET));
229 armddrclk = (reg >> armddrclk_shift) & ORION_PMISMPL_ARMDDRCLK_MASK;
230 if (model == PCI_PRODUCT_MARVELL_88F5281)
231 if (reg & ORION_PMISMPL_ARMDDRCLK_H_MASK)
232 armddrclk |= 0x00000010; /* set to bit4 */
233 for (i = 0; i < __arraycount(sysclktbl); i++)
234 if (armddrclk == sysclktbl[i].armddrclkval) {
235 mvPclk = sysclktbl[i].pclk;
236 mvSysclk = sysclktbl[i].sysclk;
237 break;
238 }
239
240 tclk = (reg >> tclk_shift) & ORION_PMISMPL_TCLK_MASK;
241 switch (tclk) {
242 case ORION_PMISMPL_TCLK_133:
243 mvTclk = 133333333; /* 133MHz */
244 break;
245
246 case ORION_PMISMPL_TCLK_150:
247 mvTclk = 150000000; /* 150MHz */
248 break;
249
250 case ORION_PMISMPL_TCLK_166:
251 mvTclk = 166666667; /* 166MHz */
252 break;
253
254 default:
255 mvTclk = 100000000; /* 100MHz */
256 break;
257 }
258 }
259