1 /* $NetBSD: mxgpu_vi.h,v 1.2 2021/12/18 23:44:59 riastradh Exp $ */ 2 3 /* 4 * Copyright 2017 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 #ifndef __MXGPU_VI_H__ 26 #define __MXGPU_VI_H__ 27 28 #define VI_MAILBOX_TIMEDOUT 12000 29 #define VI_MAILBOX_RESET_TIME 12 30 31 /* VI mailbox messages request */ 32 enum idh_request { 33 IDH_REQ_GPU_INIT_ACCESS = 1, 34 IDH_REL_GPU_INIT_ACCESS, 35 IDH_REQ_GPU_FINI_ACCESS, 36 IDH_REL_GPU_FINI_ACCESS, 37 IDH_REQ_GPU_RESET_ACCESS, 38 39 IDH_LOG_VF_ERROR = 200, 40 }; 41 42 /* VI mailbox messages data */ 43 enum idh_event { 44 IDH_CLR_MSG_BUF = 0, 45 IDH_READY_TO_ACCESS_GPU, 46 IDH_FLR_NOTIFICATION, 47 IDH_FLR_NOTIFICATION_CMPL, 48 IDH_EVENT_MAX 49 }; 50 51 extern const struct amdgpu_virt_ops xgpu_vi_virt_ops; 52 53 void xgpu_vi_init_golden_registers(struct amdgpu_device *adev); 54 void xgpu_vi_mailbox_set_irq_funcs(struct amdgpu_device *adev); 55 int xgpu_vi_mailbox_add_irq_id(struct amdgpu_device *adev); 56 int xgpu_vi_mailbox_get_irq(struct amdgpu_device *adev); 57 void xgpu_vi_mailbox_put_irq(struct amdgpu_device *adev); 58 59 #endif 60