1 /* $NetBSD: mxgpu_ai.h,v 1.2 2021/12/18 23:44:59 riastradh Exp $ */ 2 3 /* 4 * Copyright 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #ifndef __MXGPU_AI_H__ 27 #define __MXGPU_AI_H__ 28 29 #define AI_MAILBOX_POLL_ACK_TIMEDOUT 500 30 #define AI_MAILBOX_POLL_MSG_TIMEDOUT 12000 31 #define AI_MAILBOX_POLL_FLR_TIMEDOUT 500 32 33 enum idh_request { 34 IDH_REQ_GPU_INIT_ACCESS = 1, 35 IDH_REL_GPU_INIT_ACCESS, 36 IDH_REQ_GPU_FINI_ACCESS, 37 IDH_REL_GPU_FINI_ACCESS, 38 IDH_REQ_GPU_RESET_ACCESS, 39 40 IDH_LOG_VF_ERROR = 200, 41 }; 42 43 enum idh_event { 44 IDH_CLR_MSG_BUF = 0, 45 IDH_READY_TO_ACCESS_GPU, 46 IDH_FLR_NOTIFICATION, 47 IDH_FLR_NOTIFICATION_CMPL, 48 IDH_SUCCESS, 49 IDH_FAIL, 50 IDH_QUERY_ALIVE, 51 IDH_EVENT_MAX 52 }; 53 54 extern const struct amdgpu_virt_ops xgpu_ai_virt_ops; 55 56 void xgpu_ai_mailbox_set_irq_funcs(struct amdgpu_device *adev); 57 int xgpu_ai_mailbox_add_irq_id(struct amdgpu_device *adev); 58 int xgpu_ai_mailbox_get_irq(struct amdgpu_device *adev); 59 void xgpu_ai_mailbox_put_irq(struct amdgpu_device *adev); 60 61 #define AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_CONTROL) * 4 62 #define AI_MAIBOX_CONTROL_RCV_OFFSET_BYTE SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_CONTROL) * 4 + 1 63 64 #endif 65