1 /* $NetBSD: mvsocgpp.c,v 1.9 2023/06/19 08:40:29 msaitoh Exp $ */
2 /*
3 * Copyright (c) 2008, 2010 KIYOHARA Takashi
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 __KERNEL_RCSID(0, "$NetBSD: mvsocgpp.c,v 1.9 2023/06/19 08:40:29 msaitoh Exp $");
30
31 #include "gpio.h"
32
33 #define _INTR_PRIVATE
34
35 #include <sys/param.h>
36 #include <sys/bus.h>
37 #include <sys/device.h>
38 #include <sys/errno.h>
39 #include <sys/evcnt.h>
40 #include <sys/gpio.h>
41 #include <sys/kmem.h>
42
43 #include <machine/intr.h>
44
45 #include <arm/marvell/mvsocreg.h>
46 #include <arm/marvell/mvsocvar.h>
47 #include <arm/marvell/mvsocgppreg.h>
48 #include <arm/marvell/mvsocgppvar.h>
49 #include <arm/pic/picvar.h>
50
51 #include <dev/marvell/marvellvar.h>
52
53 #if NGPIO > 0
54 #include <sys/gpio.h>
55 #include <dev/gpio/gpiovar.h>
56 #endif
57
58 #define MVSOCGPP_DUMPREG
59
60 #define MVSOCGPP_READ(sc, reg) \
61 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))
62 #define MVSOCGPP_WRITE(sc, reg, val) \
63 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
64
65 struct mvsocgpp_softc {
66 device_t sc_dev;
67
68 bus_space_tag_t sc_iot;
69 bus_space_handle_t sc_ioh;
70
71 struct mvsocgpp_pic {
72 struct pic_softc gpio_pic;
73 int group;
74 int shift;
75 uint32_t edge;
76 uint32_t level;
77 } *sc_pic;
78
79 #if NGPIO > 0
80 struct gpio_chipset_tag sc_gpio_chipset;
81 gpio_pin_t *sc_pins;
82 #endif
83 };
84
85 static int mvsocgpp_match(device_t, struct cfdata *, void *);
86 static void mvsocgpp_attach(device_t, device_t, void *);
87
88 #ifdef MVSOCGPP_DUMPREG
89 static void mvsocgpp_dump_reg(struct mvsocgpp_softc *);
90 #endif
91
92 static void gpio_pic_unblock_irqs(struct pic_softc *, size_t, uint32_t);
93 static void gpio_pic_block_irqs(struct pic_softc *, size_t, uint32_t);
94 static int gpio_pic_find_pending_irqs(struct pic_softc *);
95 static void gpio_pic_establish_irq(struct pic_softc *, struct intrsource *);
96
97 static struct pic_ops gpio_pic_ops = {
98 .pic_unblock_irqs = gpio_pic_unblock_irqs,
99 .pic_block_irqs = gpio_pic_block_irqs,
100 .pic_find_pending_irqs = gpio_pic_find_pending_irqs,
101 .pic_establish_irq = gpio_pic_establish_irq,
102 };
103
104 static struct mvsocgpp_softc *mvsocgpp_softc; /* One unit per One SoC */
105 int gpp_irqbase = 0;
106 int gpp_npins = 0;
107
108
109 CFATTACH_DECL_NEW(mvsocgpp, sizeof(struct mvsocgpp_softc),
110 mvsocgpp_match, mvsocgpp_attach, NULL, NULL);
111
112
113 /* ARGSUSED */
114 static int
mvsocgpp_match(device_t parent,struct cfdata * match,void * aux)115 mvsocgpp_match(device_t parent, struct cfdata *match, void *aux)
116 {
117 struct marvell_attach_args *mva = aux;
118
119 if (strcmp(mva->mva_name, match->cf_name) != 0)
120 return 0;
121 if (mva->mva_offset == MVA_OFFSET_DEFAULT ||
122 mva->mva_irq == MVA_IRQ_DEFAULT)
123 return 0;
124
125 mva->mva_size = MVSOC_GPP_SIZE;
126 return 1;
127 }
128
129 /* ARGSUSED */
130 static void
mvsocgpp_attach(device_t parent,device_t self,void * aux)131 mvsocgpp_attach(device_t parent, device_t self, void *aux)
132 {
133 struct mvsocgpp_softc *sc = device_private(self);
134 struct marvell_attach_args *mva = aux;
135 struct pic_softc *gpio_pic;
136 #if NGPIO > 0
137 struct gpiobus_attach_args gba;
138 gpio_pin_t *pins;
139 uint32_t mask, dir, valin, valout, polarity, blink;
140 #endif
141 int i, j;
142
143 dir = valin = valout = polarity = blink = 0;
144
145 aprint_normal(": Marvell SoC General Purpose I/O Port Interface\n");
146 aprint_naive("\n");
147
148 sc->sc_dev = self;
149 sc->sc_iot = mva->mva_iot;
150 /* Map I/O registers for oriongpp */
151 if (bus_space_subregion(mva->mva_iot, mva->mva_ioh,
152 mva->mva_offset, mva->mva_size, &sc->sc_ioh)) {
153 aprint_error_dev(self, "can't map registers\n");
154 return;
155 }
156
157 if (gpp_npins > 0)
158 aprint_normal_dev(self, "%d gpio pins\n", gpp_npins);
159 else {
160 aprint_error_dev(self, "gpp_npins not initialized\n");
161 return;
162 }
163
164 mvsocgpp_softc = sc;
165
166 for (i = 0; i < gpp_npins; i += 32)
167 MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOIC(i), 0);
168
169 sc->sc_pic =
170 kmem_zalloc(sizeof(struct mvsocgpp_pic) * howmany(gpp_npins, 8),
171 KM_SLEEP);
172 for (i = 0, j = 0; i < gpp_npins; i += 8, j++) {
173 gpio_pic = &(sc->sc_pic + j)->gpio_pic;
174 gpio_pic->pic_ops = &gpio_pic_ops;
175 snprintf(gpio_pic->pic_name, sizeof(gpio_pic->pic_name),
176 "%s[%d:%d]", device_xname(self), i + 7, i);
177 gpio_pic->pic_maxsources =
178 (gpp_npins - i) > 8 ? 8 : gpp_npins - i;
179 pic_add(gpio_pic, gpp_irqbase + i);
180 aprint_normal_dev(self, "interrupts %d..%d",
181 gpp_irqbase + i, gpp_irqbase + i + 7);
182 intr_establish(mva->mva_irq + j,
183 IPL_HIGH, IST_LEVEL_HIGH, pic_handle_intr, gpio_pic);
184 aprint_normal(", intr %d\n", mva->mva_irq + j);
185
186 (sc->sc_pic + j)->group = j;
187 (sc->sc_pic + j)->shift = (j & 3) * 8;
188 }
189
190 #ifdef MVSOCGPP_DUMPREG
191 mvsocgpp_dump_reg(sc);
192 #endif
193
194 #if NGPIO > 0
195 sc->sc_pins = kmem_zalloc(sizeof(gpio_pin_t) * gpp_npins, KM_SLEEP);
196
197 for (i = 0, mask = 1; i < gpp_npins; i++, mask <<= 1) {
198 if ((i & (32 - 1)) == 0) {
199 mask = 1;
200 dir = MVSOCGPP_READ(sc, MVSOCGPP_GPIODOEC(i));
201 valin = MVSOCGPP_READ(sc, MVSOCGPP_GPIODI(i));
202 valout = MVSOCGPP_READ(sc, MVSOCGPP_GPIODO(i));
203 polarity = MVSOCGPP_READ(sc, MVSOCGPP_GPIODIP(i));
204 blink = MVSOCGPP_READ(sc, MVSOCGPP_GPIOBE(i));
205 }
206 pins = &sc->sc_pins[i];
207 pins->pin_num = i;
208 pins->pin_caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT |
209 GPIO_PIN_INVIN | GPIO_PIN_PULSATE);
210 if (dir & mask) {
211 pins->pin_flags = GPIO_PIN_INPUT;
212 pins->pin_state =
213 (valin & mask) ? GPIO_PIN_HIGH : GPIO_PIN_LOW;
214 } else {
215 pins->pin_flags = GPIO_PIN_OUTPUT;
216 pins->pin_state =
217 (valout & mask) ? GPIO_PIN_HIGH : GPIO_PIN_LOW;
218 }
219 if (polarity & mask) {
220 pins->pin_flags |= GPIO_PIN_INVIN;
221 }
222 if (blink & mask) {
223 pins->pin_flags |= GPIO_PIN_PULSATE;
224 }
225 }
226 sc->sc_gpio_chipset.gp_cookie = sc;
227 sc->sc_gpio_chipset.gp_pin_read = mvsocgpp_pin_read;
228 sc->sc_gpio_chipset.gp_pin_write = mvsocgpp_pin_write;
229 sc->sc_gpio_chipset.gp_pin_ctl = mvsocgpp_pin_ctl;
230 gba.gba_gc = &sc->sc_gpio_chipset;
231 gba.gba_pins = sc->sc_pins;
232 gba.gba_npins = gpp_npins;
233 config_found(self, &gba, gpiobus_print, CFARGS_NONE);
234 #endif
235 }
236
237 /*
238 * arch/arm/pic functions.
239 */
240
241 static void
gpio_pic_unblock_irqs(struct pic_softc * pic,size_t irqbase,uint32_t irq_mask)242 gpio_pic_unblock_irqs(struct pic_softc *pic, size_t irqbase, uint32_t irq_mask)
243 {
244 struct mvsocgpp_softc *sc = mvsocgpp_softc;
245 struct mvsocgpp_pic *mvsocgpp_pic = (struct mvsocgpp_pic *)pic;
246 uint32_t mask;
247 int pin = mvsocgpp_pic->group << 3;
248
249 irq_mask = irq_mask << mvsocgpp_pic->shift;
250 MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOIC(pin),
251 MVSOCGPP_READ(sc, MVSOCGPP_GPIOIC(pin)) & ~irq_mask);
252 if (irq_mask & mvsocgpp_pic->edge) {
253 mask = MVSOCGPP_READ(sc, MVSOCGPP_GPIOIM(pin));
254 mask |= (irq_mask & mvsocgpp_pic->edge);
255 MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOIM(pin), mask);
256 }
257 if (irq_mask & mvsocgpp_pic->level) {
258 mask = MVSOCGPP_READ(sc, MVSOCGPP_GPIOILM(pin));
259 mask |= (irq_mask & mvsocgpp_pic->level);
260 MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOILM(pin), mask);
261 }
262 }
263
264 /* ARGSUSED */
265 static void
gpio_pic_block_irqs(struct pic_softc * pic,size_t irqbase,uint32_t irq_mask)266 gpio_pic_block_irqs(struct pic_softc *pic, size_t irqbase, uint32_t irq_mask)
267 {
268 struct mvsocgpp_softc *sc = mvsocgpp_softc;
269 struct mvsocgpp_pic *mvsocgpp_pic = (struct mvsocgpp_pic *)pic;
270 int pin = mvsocgpp_pic->group << 3;
271
272 irq_mask = irq_mask << mvsocgpp_pic->shift;
273 MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOIM(pin),
274 MVSOCGPP_READ(sc, MVSOCGPP_GPIOIM(pin)) & ~irq_mask);
275 MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOILM(pin),
276 MVSOCGPP_READ(sc, MVSOCGPP_GPIOILM(pin)) & ~irq_mask);
277 }
278
279 static int
gpio_pic_find_pending_irqs(struct pic_softc * pic)280 gpio_pic_find_pending_irqs(struct pic_softc *pic)
281 {
282 struct mvsocgpp_softc *sc = mvsocgpp_softc;
283 struct mvsocgpp_pic *mvsocgpp_pic = (struct mvsocgpp_pic *)pic;
284 uint32_t pending;
285 int pin = mvsocgpp_pic->group << 3;
286
287 pending = MVSOCGPP_READ(sc, MVSOCGPP_GPIOIC(pin));
288 pending &= (0xff << mvsocgpp_pic->shift);
289 pending &= (MVSOCGPP_READ(sc, MVSOCGPP_GPIOIM(pin)) |
290 MVSOCGPP_READ(sc, MVSOCGPP_GPIOILM(pin)));
291 pending = pending >> mvsocgpp_pic->shift;
292
293 if (pending == 0)
294 return 0;
295
296 return pic_mark_pending_sources(pic, 0, pending);
297 }
298
299 static void
gpio_pic_establish_irq(struct pic_softc * pic,struct intrsource * is)300 gpio_pic_establish_irq(struct pic_softc *pic, struct intrsource *is)
301 {
302 struct mvsocgpp_softc *sc = mvsocgpp_softc;
303 struct mvsocgpp_pic *mvsocgpp_pic = (struct mvsocgpp_pic *)pic;
304 uint32_t im, ilm, mask;
305 int type, pin;
306
307 type = is->is_type;
308 pin = pic->pic_irqbase + is->is_irq - gpp_irqbase;
309 mask = MVSOCGPP_GPIOPIN(pin);
310
311 switch (type) {
312 case IST_LEVEL_LOW:
313 case IST_EDGE_FALLING:
314 mvsocgpp_pin_ctl(NULL, pin, GPIO_PIN_INPUT | GPIO_PIN_INVIN);
315 break;
316
317 case IST_LEVEL_HIGH:
318 case IST_EDGE_RISING:
319 mvsocgpp_pin_ctl(NULL, pin, GPIO_PIN_INPUT);
320 break;
321
322 default:
323 panic("unknown interrupt type %d for pin %d.\n", type, pin);
324 }
325
326 im = MVSOCGPP_READ(sc, MVSOCGPP_GPIOIM(pin));
327 ilm = MVSOCGPP_READ(sc, MVSOCGPP_GPIOILM(pin));
328 switch (type) {
329 case IST_EDGE_FALLING:
330 case IST_EDGE_RISING:
331 im |= mask;
332 ilm &= ~mask;
333 mvsocgpp_pic->edge |= mask;
334 mvsocgpp_pic->level &= ~mask;
335 break;
336
337 case IST_LEVEL_LOW:
338 case IST_LEVEL_HIGH:
339 im &= ~mask;
340 ilm |= mask;
341 mvsocgpp_pic->edge &= ~mask;
342 mvsocgpp_pic->level |= mask;
343 break;
344 }
345 MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOIM(pin), im);
346 MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOILM(pin), ilm);
347 }
348
349
350 /*
351 * gpio(4) functions, and can call you.
352 */
353
354 /* ARGSUSED */
355 int
mvsocgpp_pin_read(void * arg,int pin)356 mvsocgpp_pin_read(void *arg, int pin)
357 {
358 struct mvsocgpp_softc *sc = mvsocgpp_softc;
359 uint32_t val;
360
361 KASSERT(sc != NULL);
362
363 val = MVSOCGPP_READ(sc, MVSOCGPP_GPIODI(pin));
364 return (val & MVSOCGPP_GPIOPIN(pin)) != 0;
365 }
366
367 /* ARGSUSED */
368 void
mvsocgpp_pin_write(void * arg,int pin,int value)369 mvsocgpp_pin_write(void *arg, int pin, int value)
370 {
371 struct mvsocgpp_softc *sc = mvsocgpp_softc;
372 uint32_t old, new, mask = MVSOCGPP_GPIOPIN(pin);
373
374 KASSERT(sc != NULL);
375
376 old = MVSOCGPP_READ(sc, MVSOCGPP_GPIODO(pin));
377 if (value)
378 new = old | mask;
379 else
380 new = old & ~mask;
381 if (new != old)
382 MVSOCGPP_WRITE(sc, MVSOCGPP_GPIODO(pin), new);
383 }
384
385 /* ARGSUSED */
386 void
mvsocgpp_pin_ctl(void * arg,int pin,int flags)387 mvsocgpp_pin_ctl(void *arg, int pin, int flags)
388 {
389 struct mvsocgpp_softc *sc = mvsocgpp_softc;
390 uint32_t old, new, mask = MVSOCGPP_GPIOPIN(pin);
391
392 KASSERT(sc != NULL);
393
394 old = MVSOCGPP_READ(sc, MVSOCGPP_GPIODOEC(pin));
395 switch (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
396 case GPIO_PIN_INPUT:
397 new = old | mask;
398 break;
399
400 case GPIO_PIN_OUTPUT:
401 new = old & ~mask;
402 break;
403
404 default:
405 return;
406 }
407 if (new != old)
408 MVSOCGPP_WRITE(sc, MVSOCGPP_GPIODOEC(pin), new);
409
410 /* Blink every 2^24 TCLK */
411 old = MVSOCGPP_READ(sc, MVSOCGPP_GPIOBE(pin));
412 if (flags & GPIO_PIN_PULSATE)
413 new = old | mask;
414 else
415 new = old & ~mask;
416 if (new != old)
417 MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOBE(pin), new);
418
419 old = MVSOCGPP_READ(sc, MVSOCGPP_GPIODIP(pin));
420 if (flags & GPIO_PIN_INVIN)
421 new = old | mask;
422 else
423 new = old & ~mask;
424 if (new != old)
425 MVSOCGPP_WRITE(sc, MVSOCGPP_GPIODIP(pin), new);
426 }
427
428
429 #ifdef MVSOCGPP_DUMPREG
430 static void
mvsocgpp_dump_reg(struct mvsocgpp_softc * sc)431 mvsocgpp_dump_reg(struct mvsocgpp_softc *sc)
432 {
433
434 aprint_normal_dev(sc->sc_dev, " Data Out: \t0x%08x\n",
435 MVSOCGPP_READ(sc, MVSOCGPP_GPIODO(0)));
436 aprint_normal_dev(sc->sc_dev, " Data Out Enable Control: \t0x%08x\n",
437 MVSOCGPP_READ(sc, MVSOCGPP_GPIODOEC(0)));
438 aprint_normal_dev(sc->sc_dev, " Data Blink Enable: \t0x%08x\n",
439 MVSOCGPP_READ(sc, MVSOCGPP_GPIOBE(0)));
440 aprint_normal_dev(sc->sc_dev, " Data In Polarity: \t0x%08x\n",
441 MVSOCGPP_READ(sc, MVSOCGPP_GPIODIP(0)));
442 aprint_normal_dev(sc->sc_dev, " Data In: \t0x%08x\n",
443 MVSOCGPP_READ(sc, MVSOCGPP_GPIODI(0)));
444 aprint_normal_dev(sc->sc_dev, " Interrupt Cause: \t0x%08x\n",
445 MVSOCGPP_READ(sc, MVSOCGPP_GPIOIC(0)));
446 aprint_normal_dev(sc->sc_dev, " Interrupt Mask: \t0x%08x\n",
447 MVSOCGPP_READ(sc, MVSOCGPP_GPIOIM(0)));
448 aprint_normal_dev(sc->sc_dev, " Interrupt Level Mask: \t0x%08x\n",
449 MVSOCGPP_READ(sc, MVSOCGPP_GPIOILM(0)));
450
451 if (gpp_npins <= 32)
452 return;
453
454 aprint_normal_dev(sc->sc_dev, " High Data Out: \t0x%08x\n",
455 MVSOCGPP_READ(sc, MVSOCGPP_GPIODO(32)));
456 aprint_normal_dev(sc->sc_dev, " High Data Out Enable Ctrl:\t0x%08x\n",
457 MVSOCGPP_READ(sc, MVSOCGPP_GPIODOEC(32)));
458 aprint_normal_dev(sc->sc_dev, " High Blink Enable: \t0x%08x\n",
459 MVSOCGPP_READ(sc, MVSOCGPP_GPIOBE(32)));
460 aprint_normal_dev(sc->sc_dev, " High Data In Polarity: \t0x%08x\n",
461 MVSOCGPP_READ(sc, MVSOCGPP_GPIODIP(32)));
462 aprint_normal_dev(sc->sc_dev, " High Data In: \t0x%08x\n",
463 MVSOCGPP_READ(sc, MVSOCGPP_GPIODI(32)));
464 aprint_normal_dev(sc->sc_dev, " High Interrupt Cause: \t0x%08x\n",
465 MVSOCGPP_READ(sc, MVSOCGPP_GPIOIC(32)));
466 aprint_normal_dev(sc->sc_dev, " High Interrupt Mask: \t0x%08x\n",
467 MVSOCGPP_READ(sc, MVSOCGPP_GPIOIM(32)));
468 aprint_normal_dev(sc->sc_dev, " High Interrupt Level Mask:\t0x%08x\n",
469 MVSOCGPP_READ(sc, MVSOCGPP_GPIOILM(32)));
470 }
471 #endif
472