xref: /netbsd-src/sys/arch/alpha/alpha/multiproc.s (revision a82352701eb9b96cfd52e04ad877e173992eaccb)
1/* $NetBSD: multiproc.s,v 1.15 2020/09/04 03:53:12 thorpej Exp $ */
2
3/*-
4 * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 * NASA Ames Research Center.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 *    notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 *    notice, this list of conditions and the following disclaimer in the
18 *    documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
31 */
32
33__KERNEL_RCSID(5, "$NetBSD: multiproc.s,v 1.15 2020/09/04 03:53:12 thorpej Exp $")
34
35/*
36 * Multiprocessor glue code.
37 */
38
39	.text
40inc5:	.stabs	__FILE__,132,0,0,inc5; .loc	1 __LINE__
41
42/*
43 * cpu_spinup_trampoline:
44 *
45 * We come here via the secondary processor's console.  We simply
46 * make the function call look right, and call cpu_hatch() to finish
47 * starting up the processor.
48 *
49 * We are provided an argument in $27 (pv).  It will be a pointer to
50 * our cpu_info.
51 */
52NESTED_NOPROFILE(cpu_spinup_trampoline,0,0,ra,0,0)
53	mov	pv, s0			/* squirrel away argument */
54
55	br	pv, 1f			/* compute new GP */
561:	LDGP(pv)
57
58	/* Write new KGP. */
59	mov	gp, a0
60	call_pal PAL_OSF1_wrkgp
61
62	/* Make sure the cpu_info and lwp reference each other. */
63	ldq	s1, CPU_INFO_IDLE_LWP(s0)
64	stq	s0, L_CPU(s1)		/* set lwp::l_cpu */
65
66	/* Switch to this CPU's idle thread. */
67	ldq	a0, L_MD_PCBPADDR(s1)
68	call_pal PAL_OSF1_swpctx
69
70	SET_CURLWP(s1)
71
72	/* Invalidate TLB and I-stream. */
73	ldiq	a0, -2			/* TBIA */
74	call_pal PAL_OSF1_tbi
75	call_pal PAL_imb
76
77	/* Make sure the FPU is turned off. */
78	mov	zero, a0
79	call_pal PAL_OSF1_wrfen
80
81	/* Restore argument and call cpu_hatch() */
82	mov	s0, a0
83	CALL(cpu_hatch)
84
85	/* enable all interrupts */
86	mov	zero, a0
87	call_pal PAL_OSF1_swpipl
88	/* Jump into the idle loop! */
89	jmp	zero, idle_loop
90
91	END(cpu_spinup_trampoline)
92