1 /* $NetBSD: mmio.c,v 1.2 2021/12/18 23:45:31 riastradh Exp $ */
2
3 /*
4 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Ke Yu
27 * Kevin Tian <kevin.tian@intel.com>
28 * Dexuan Cui
29 *
30 * Contributors:
31 * Tina Zhang <tina.zhang@intel.com>
32 * Min He <min.he@intel.com>
33 * Niu Bing <bing.niu@intel.com>
34 * Zhi Wang <zhi.a.wang@intel.com>
35 *
36 */
37
38 #include <sys/cdefs.h>
39 __KERNEL_RCSID(0, "$NetBSD: mmio.c,v 1.2 2021/12/18 23:45:31 riastradh Exp $");
40
41 #include "i915_drv.h"
42 #include "gvt.h"
43
44 /**
45 * intel_vgpu_gpa_to_mmio_offset - translate a GPA to MMIO offset
46 * @vgpu: a vGPU
47 * @gpa: guest physical address
48 *
49 * Returns:
50 * Zero on success, negative error code if failed
51 */
intel_vgpu_gpa_to_mmio_offset(struct intel_vgpu * vgpu,u64 gpa)52 int intel_vgpu_gpa_to_mmio_offset(struct intel_vgpu *vgpu, u64 gpa)
53 {
54 u64 gttmmio_gpa = intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_0);
55 return gpa - gttmmio_gpa;
56 }
57
58 #define reg_is_mmio(gvt, reg) \
59 (reg >= 0 && reg < gvt->device_info.mmio_size)
60
61 #define reg_is_gtt(gvt, reg) \
62 (reg >= gvt->device_info.gtt_start_offset \
63 && reg < gvt->device_info.gtt_start_offset + gvt_ggtt_sz(gvt))
64
failsafe_emulate_mmio_rw(struct intel_vgpu * vgpu,u64 pa,void * p_data,unsigned int bytes,bool read)65 static void failsafe_emulate_mmio_rw(struct intel_vgpu *vgpu, u64 pa,
66 void *p_data, unsigned int bytes, bool read)
67 {
68 struct intel_gvt *gvt = NULL;
69 void *pt = NULL;
70 unsigned int offset = 0;
71
72 if (!vgpu || !p_data)
73 return;
74
75 gvt = vgpu->gvt;
76 mutex_lock(&vgpu->vgpu_lock);
77 offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
78 if (reg_is_mmio(gvt, offset)) {
79 if (read)
80 intel_vgpu_default_mmio_read(vgpu, offset, p_data,
81 bytes);
82 else
83 intel_vgpu_default_mmio_write(vgpu, offset, p_data,
84 bytes);
85 } else if (reg_is_gtt(gvt, offset)) {
86 offset -= gvt->device_info.gtt_start_offset;
87 pt = vgpu->gtt.ggtt_mm->ggtt_mm.virtual_ggtt + offset;
88 if (read)
89 memcpy(p_data, pt, bytes);
90 else
91 memcpy(pt, p_data, bytes);
92
93 }
94 mutex_unlock(&vgpu->vgpu_lock);
95 }
96
97 /**
98 * intel_vgpu_emulate_mmio_read - emulate MMIO read
99 * @vgpu: a vGPU
100 * @pa: guest physical address
101 * @p_data: data return buffer
102 * @bytes: access data length
103 *
104 * Returns:
105 * Zero on success, negative error code if failed
106 */
intel_vgpu_emulate_mmio_read(struct intel_vgpu * vgpu,u64 pa,void * p_data,unsigned int bytes)107 int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, u64 pa,
108 void *p_data, unsigned int bytes)
109 {
110 struct intel_gvt *gvt = vgpu->gvt;
111 unsigned int offset = 0;
112 int ret = -EINVAL;
113
114 if (vgpu->failsafe) {
115 failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, true);
116 return 0;
117 }
118 mutex_lock(&vgpu->vgpu_lock);
119
120 offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
121
122 if (WARN_ON(bytes > 8))
123 goto err;
124
125 if (reg_is_gtt(gvt, offset)) {
126 if (WARN_ON(!IS_ALIGNED(offset, 4) && !IS_ALIGNED(offset, 8)))
127 goto err;
128 if (WARN_ON(bytes != 4 && bytes != 8))
129 goto err;
130 if (WARN_ON(!reg_is_gtt(gvt, offset + bytes - 1)))
131 goto err;
132
133 ret = intel_vgpu_emulate_ggtt_mmio_read(vgpu, offset,
134 p_data, bytes);
135 if (ret)
136 goto err;
137 goto out;
138 }
139
140 if (WARN_ON_ONCE(!reg_is_mmio(gvt, offset))) {
141 ret = intel_gvt_hypervisor_read_gpa(vgpu, pa, p_data, bytes);
142 goto out;
143 }
144
145 if (WARN_ON(!reg_is_mmio(gvt, offset + bytes - 1)))
146 goto err;
147
148 if (!intel_gvt_mmio_is_unalign(gvt, offset)) {
149 if (WARN_ON(!IS_ALIGNED(offset, bytes)))
150 goto err;
151 }
152
153 ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, true);
154 if (ret < 0)
155 goto err;
156
157 intel_gvt_mmio_set_accessed(gvt, offset);
158 ret = 0;
159 goto out;
160
161 err:
162 gvt_vgpu_err("fail to emulate MMIO read %08x len %d\n",
163 offset, bytes);
164 out:
165 mutex_unlock(&vgpu->vgpu_lock);
166 return ret;
167 }
168
169 /**
170 * intel_vgpu_emulate_mmio_write - emulate MMIO write
171 * @vgpu: a vGPU
172 * @pa: guest physical address
173 * @p_data: write data buffer
174 * @bytes: access data length
175 *
176 * Returns:
177 * Zero on success, negative error code if failed
178 */
intel_vgpu_emulate_mmio_write(struct intel_vgpu * vgpu,u64 pa,void * p_data,unsigned int bytes)179 int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, u64 pa,
180 void *p_data, unsigned int bytes)
181 {
182 struct intel_gvt *gvt = vgpu->gvt;
183 unsigned int offset = 0;
184 int ret = -EINVAL;
185
186 if (vgpu->failsafe) {
187 failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, false);
188 return 0;
189 }
190
191 mutex_lock(&vgpu->vgpu_lock);
192
193 offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
194
195 if (WARN_ON(bytes > 8))
196 goto err;
197
198 if (reg_is_gtt(gvt, offset)) {
199 if (WARN_ON(!IS_ALIGNED(offset, 4) && !IS_ALIGNED(offset, 8)))
200 goto err;
201 if (WARN_ON(bytes != 4 && bytes != 8))
202 goto err;
203 if (WARN_ON(!reg_is_gtt(gvt, offset + bytes - 1)))
204 goto err;
205
206 ret = intel_vgpu_emulate_ggtt_mmio_write(vgpu, offset,
207 p_data, bytes);
208 if (ret)
209 goto err;
210 goto out;
211 }
212
213 if (WARN_ON_ONCE(!reg_is_mmio(gvt, offset))) {
214 ret = intel_gvt_hypervisor_write_gpa(vgpu, pa, p_data, bytes);
215 goto out;
216 }
217
218 ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, false);
219 if (ret < 0)
220 goto err;
221
222 intel_gvt_mmio_set_accessed(gvt, offset);
223 ret = 0;
224 goto out;
225 err:
226 gvt_vgpu_err("fail to emulate MMIO write %08x len %d\n", offset,
227 bytes);
228 out:
229 mutex_unlock(&vgpu->vgpu_lock);
230 return ret;
231 }
232
233
234 /**
235 * intel_vgpu_reset_mmio - reset virtual MMIO space
236 * @vgpu: a vGPU
237 * @dmlr: whether this is device model level reset
238 */
intel_vgpu_reset_mmio(struct intel_vgpu * vgpu,bool dmlr)239 void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr)
240 {
241 struct intel_gvt *gvt = vgpu->gvt;
242 const struct intel_gvt_device_info *info = &gvt->device_info;
243 void *mmio = gvt->firmware.mmio;
244
245 if (dmlr) {
246 memcpy(vgpu->mmio.vreg, mmio, info->mmio_size);
247
248 vgpu_vreg_t(vgpu, GEN6_GT_THREAD_STATUS_REG) = 0;
249
250 /* set the bit 0:2(Core C-State ) to C0 */
251 vgpu_vreg_t(vgpu, GEN6_GT_CORE_STATUS) = 0;
252
253 if (IS_BROXTON(vgpu->gvt->dev_priv)) {
254 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &=
255 ~(BIT(0) | BIT(1));
256 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
257 ~PHY_POWER_GOOD;
258 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=
259 ~PHY_POWER_GOOD;
260 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &=
261 ~BIT(30);
262 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &=
263 ~BIT(30);
264 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &=
265 ~BXT_PHY_LANE_ENABLED;
266 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |=
267 BXT_PHY_CMNLANE_POWERDOWN_ACK |
268 BXT_PHY_LANE_POWERDOWN_ACK;
269 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &=
270 ~BXT_PHY_LANE_ENABLED;
271 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |=
272 BXT_PHY_CMNLANE_POWERDOWN_ACK |
273 BXT_PHY_LANE_POWERDOWN_ACK;
274 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &=
275 ~BXT_PHY_LANE_ENABLED;
276 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |=
277 BXT_PHY_CMNLANE_POWERDOWN_ACK |
278 BXT_PHY_LANE_POWERDOWN_ACK;
279 }
280 } else {
281 #define GVT_GEN8_MMIO_RESET_OFFSET (0x44200)
282 /* only reset the engine related, so starting with 0x44200
283 * interrupt include DE,display mmio related will not be
284 * touched
285 */
286 memcpy(vgpu->mmio.vreg, mmio, GVT_GEN8_MMIO_RESET_OFFSET);
287 }
288
289 }
290
291 /**
292 * intel_vgpu_init_mmio - init MMIO space
293 * @vgpu: a vGPU
294 *
295 * Returns:
296 * Zero on success, negative error code if failed
297 */
intel_vgpu_init_mmio(struct intel_vgpu * vgpu)298 int intel_vgpu_init_mmio(struct intel_vgpu *vgpu)
299 {
300 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
301
302 vgpu->mmio.vreg = vzalloc(info->mmio_size);
303 if (!vgpu->mmio.vreg)
304 return -ENOMEM;
305
306 intel_vgpu_reset_mmio(vgpu, true);
307
308 return 0;
309 }
310
311 /**
312 * intel_vgpu_clean_mmio - clean MMIO space
313 * @vgpu: a vGPU
314 *
315 */
intel_vgpu_clean_mmio(struct intel_vgpu * vgpu)316 void intel_vgpu_clean_mmio(struct intel_vgpu *vgpu)
317 {
318 vfree(vgpu->mmio.vreg);
319 vgpu->mmio.vreg = NULL;
320 }
321