xref: /netbsd-src/sys/arch/hpc/stand/hpcboot/mips/mips_arch.h (revision f0dcd50e0ea5f1222ec4c7a8741a1744d0850ddf)
1 /* -*-C++-*-	$NetBSD: mips_arch.h,v 1.7 2023/08/10 06:44:11 andvar Exp $	*/
2 
3 /*-
4  * Copyright (c) 2001 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by UCHIYAMA Yasushi.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31 
32 #ifndef _HPCBOOT_MIPS_ARCH_H_
33 #define	_HPCBOOT_MIPS_ARCH_H_
34 
35 #include <hpcboot.h>
36 #include <arch.h>
37 
38 class Console;
39 
40 class MIPSArchitecture : public Architecture {
41 protected:
42 	typedef void(*boot_func_t)(struct BootArgs *, struct PageTag *);
43 
44 	int _kmode;
45 	boot_func_t _boot_func;
46 
47 public:
48 	MIPSArchitecture(Console *&, MemoryManager *&);
49 	virtual ~MIPSArchitecture(void);
50 
51 	virtual BOOL init(void);
52 	BOOL setupLoader(void);
53 	virtual void systemInfo(void);
54 	virtual void cacheFlush(void) = 0;
55 	void jump(paddr_t info, paddr_t pvec);
56 };
57 
58 #define	DI()								\
59   __asm(".set noreorder;"						\
60 	 "nop;"								\
61 	 "mtc0	zero, $12;"						\
62 	 "nop;nop;nop;" /* CP0 hazard for R4000 */			\
63 	 ".set reorder")
64 
65 #define	GET_SR(x)							\
66   __asm(".set noreorder;"						\
67 	 "mfc0	t0, $12;"						\
68 	 "sw	t0,(%0);"						\
69 	 ".set reorder", &(x));
70 
71 #define	SET_SR(x)							\
72   __asm(".set noreorder;"						\
73 	 "lw	t0,(%0);"						\
74 	 "nop;"								\
75 	 "mtc0	t0, $12;"						\
76 	 "nop;nop;nop;" /* CP0 hazard for R4000 */			\
77 	 ".set reorder", &(x));
78 
79 /*
80  * 2nd-bootloader.  make sure that PIC and its size is lower than page size.
81  * and can't call subroutine.
82  * naked function can't use stack. if you want to use, remove its declare.
83  * interrupts are disabled. but if access kuseg,(should not occur)
84  * it causes TLB exception and then Windows CE enable interrupts again.
85  */
86 #define	BOOT_FUNC_(x)							\
87 __declspec(naked) void							\
88 x##::boot_func(struct BootArgs *bi, struct PageTag *p)			\
89 {									\
90   /* disable interrupt */						\
91   DI();									\
92   /* set kernel image */						\
93   __asm(".set noreorder;"						\
94 	 "move	t6, a1;"	/* p */					\
95 	 "li	t1, 0xffffffff;"					\
96 "page_start:"								\
97 	 "beq	t6, t1, page_end;"					\
98 	 "move	t7, t6;"						\
99 	 "lw	t6, 0(t7);"	/* p = next */				\
100 	 "lw	t0, 4(t7);"	/* src */				\
101 	 "lw	t4, 8(t7);"	/* dst */				\
102 	 "lw	t2, 12(t7);"	/* sz */				\
103 	 "beq	t0, t1, page_clear;"					\
104 	 "addu	t5, t4, t2;"	/* dst + sz */				\
105 "page_copy:"								\
106 	 "lw	t3, 0(t0);"	/* bcopy */				\
107 	 "sw	t3, 0(t4);"						\
108 	 "addiu	t4, t4, 4;"						\
109 	 "bltu	t4, t5, page_copy;"					\
110 	 "addiu	t0, t0, 4;"						\
111 	 "b	page_start;"						\
112 	 "nop;"								\
113 "page_clear:"								\
114 	 "sw	zero, 0(t4);"	/* bzero */				\
115 	 "addiu	t4, t4, 4;"						\
116 	 "bltu	t4, t5, page_clear;"					\
117 	 "nop;"								\
118 	 "b	page_start;"						\
119 	 "nop;"								\
120 "page_end:"								\
121 	 "nop;"								\
122 	 ".set reorder");						\
123 									\
124   /* Cache flush for kernel */						\
125   MIPS_##x##_CACHE_FLUSH();						\
126 									\
127   /* jump to kernel entry */						\
128   __asm(".set noreorder;"						\
129 	 "move	t0, a0;"						\
130 	 "lw	t1, 0(t0);"						\
131 	 "lw	a0, 4(t0);"						\
132 	 "lw	a1, 8(t0);"						\
133 	 "lw	a2, 12(t0);"						\
134 	 "jr	t1;"							\
135 	 "nop;"								\
136 	 ".set reorder");						\
137 }
138 
139 #endif // _HPCBOOT_MIPS_ARCH_H_
140