1 /* $NetBSD: meson_usbphy.c,v 1.6 2021/01/27 03:10:18 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2019 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30
31 __KERNEL_RCSID(0, "$NetBSD: meson_usbphy.c,v 1.6 2021/01/27 03:10:18 thorpej Exp $");
32
33 #include <sys/param.h>
34 #include <sys/bus.h>
35 #include <sys/device.h>
36 #include <sys/intr.h>
37 #include <sys/systm.h>
38 #include <sys/time.h>
39
40 #include <dev/fdt/fdtvar.h>
41
42 #define CBUS_REG(x) ((x) << 2)
43 #define PREI_USB_PHY_CFG_REG CBUS_REG(0x00)
44 #define PREI_USB_PHY_CFG_CLK_32K_ALT_SEL __BIT(15)
45 #define PREI_USB_PHY_CTRL_REG CBUS_REG(0x01)
46 #define PREI_USB_PHY_CTRL_FSEL __BITS(24,22)
47 #define PREI_USB_PHY_CTRL_FSEL_24M 5
48 #define PREI_USB_PHY_CTRL_FSEL_12M 2
49 #define PREI_USB_PHY_CTRL_POR __BIT(15)
50 #define PREI_USB_PHY_CTRL_CLK_DET __BIT(8)
51 #define PREI_USB_PHY_ADP_BC_REG CBUS_REG(0x03)
52 #define PREI_USB_PHY_ADP_BC_ACA_FLOATING __BIT(26)
53 #define PREI_USB_PHY_ADP_BC_ACA_ENABLE __BIT(16)
54
55 static int meson_usbphy_match(device_t, cfdata_t, void *);
56 static void meson_usbphy_attach(device_t, device_t, void *);
57
58 enum meson_usbphy_type {
59 USBPHY_MESON8B,
60 };
61
62 static const struct device_compatible_entry compat_data[] = {
63 { .compat = "amlogic,meson8b-usb2-phy",
64 .value = USBPHY_MESON8B },
65 { .compat = "amlogic,meson-gxbb-usb2-phy",
66 .value = USBPHY_MESON8B },
67
68 DEVICE_COMPAT_EOL
69 };
70
71 struct meson_usbphy_softc {
72 device_t sc_dev;
73 bus_space_tag_t sc_bst;
74 bus_space_handle_t sc_bsh;
75 int sc_phandle;
76 const char *sc_dr_mode;
77 enum meson_usbphy_type sc_type;
78 };
79
80 #define PHY_READ(sc, reg) \
81 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
82 #define PHY_WRITE(sc, reg, val) \
83 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
84
85 CFATTACH_DECL_NEW(meson_usbphy, sizeof(struct meson_usbphy_softc),
86 meson_usbphy_match, meson_usbphy_attach, NULL, NULL);
87
88 static const char *
meson_usbphy_dr_mode(struct meson_usbphy_softc * sc)89 meson_usbphy_dr_mode(struct meson_usbphy_softc *sc)
90 {
91 int index, phandle;
92
93 index = 0;
94 while ((phandle = fdt_find_with_property("phys", &index)) != -1) {
95 const int phy_phandle = fdtbus_get_phandle(phandle, "phys");
96 if (phy_phandle != sc->sc_phandle)
97 continue;
98 return fdtbus_get_string(phandle, "dr_mode");
99 }
100
101 return NULL;
102 }
103
104 static void *
meson_usbphy_acquire(device_t dev,const void * data,size_t len)105 meson_usbphy_acquire(device_t dev, const void *data, size_t len)
106 {
107 if (len != 0)
108 return NULL;
109
110 return (void *)(uintptr_t)1;
111 }
112
113 static void
meson_usbphy_release(device_t dev,void * priv)114 meson_usbphy_release(device_t dev, void *priv)
115 {
116 }
117
118 static int
meson_usbphy_enable(device_t dev,void * priv,bool enable)119 meson_usbphy_enable(device_t dev, void *priv, bool enable)
120 {
121 struct meson_usbphy_softc * const sc = device_private(dev);
122 struct fdtbus_regulator *reg;
123 uint32_t val;
124 int error;
125
126 if (enable) {
127 if (of_hasprop(sc->sc_phandle, "phy-supply")) {
128 reg = fdtbus_regulator_acquire(sc->sc_phandle, "phy-supply");
129 if (reg != NULL) {
130 error = fdtbus_regulator_enable(reg);
131 if (error != 0)
132 device_printf(dev, "WARNING: couldn't enable phy-supply: %d\n", error);
133 } else {
134 device_printf(dev, "WARNING: couldn't acquire phy-supply\n");
135 }
136 }
137
138 delay(1000);
139
140 val = PHY_READ(sc, PREI_USB_PHY_CFG_REG);
141 val |= PREI_USB_PHY_CFG_CLK_32K_ALT_SEL;
142 PHY_WRITE(sc, PREI_USB_PHY_CFG_REG, val);
143
144 val = PHY_READ(sc, PREI_USB_PHY_CTRL_REG);
145 val &= ~PREI_USB_PHY_CTRL_FSEL;
146 val |= __SHIFTIN(PREI_USB_PHY_CTRL_FSEL_24M,
147 PREI_USB_PHY_CTRL_FSEL);
148 val |= PREI_USB_PHY_CTRL_POR;
149 PHY_WRITE(sc, PREI_USB_PHY_CTRL_REG, val);
150
151 delay(1000);
152
153 val = PHY_READ(sc, PREI_USB_PHY_CTRL_REG);
154 val &= ~PREI_USB_PHY_CTRL_POR;
155 PHY_WRITE(sc, PREI_USB_PHY_CTRL_REG, val);
156
157 delay(50000);
158
159 val = PHY_READ(sc, PREI_USB_PHY_CTRL_REG);
160 if ((val & PREI_USB_PHY_CTRL_CLK_DET) == 0)
161 aprint_error_dev(dev, "WARNING: USB PHY clock not detected\n");
162
163 if (sc->sc_dr_mode && strcmp(sc->sc_dr_mode, "host") == 0) {
164 val = PHY_READ(sc, PREI_USB_PHY_ADP_BC_REG);
165 val |= PREI_USB_PHY_ADP_BC_ACA_ENABLE;
166 PHY_WRITE(sc, PREI_USB_PHY_ADP_BC_REG, val);
167
168 delay(1000);
169
170 val = PHY_READ(sc, PREI_USB_PHY_ADP_BC_REG);
171 if ((val & PREI_USB_PHY_ADP_BC_ACA_FLOATING) != 0)
172 aprint_error_dev(dev, "WARNING: USB PHY failed to enable ACA detection\n");
173 }
174 }
175
176 return 0;
177 }
178
179 const struct fdtbus_phy_controller_func meson_usbphy_funcs = {
180 .acquire = meson_usbphy_acquire,
181 .release = meson_usbphy_release,
182 .enable = meson_usbphy_enable,
183 };
184
185 static int
meson_usbphy_match(device_t parent,cfdata_t cf,void * aux)186 meson_usbphy_match(device_t parent, cfdata_t cf, void *aux)
187 {
188 struct fdt_attach_args * const faa = aux;
189
190 return of_compatible_match(faa->faa_phandle, compat_data);
191 }
192
193 static void
meson_usbphy_attach(device_t parent,device_t self,void * aux)194 meson_usbphy_attach(device_t parent, device_t self, void *aux)
195 {
196 struct meson_usbphy_softc * const sc = device_private(self);
197 struct fdt_attach_args * const faa = aux;
198 const int phandle = faa->faa_phandle;
199 struct fdtbus_reset *rst;
200 struct clk *clk;
201 bus_addr_t addr;
202 bus_size_t size;
203 u_int n;
204
205 sc->sc_dev = self;
206 sc->sc_bst = faa->faa_bst;
207 sc->sc_phandle = phandle;
208 sc->sc_type = of_compatible_lookup(phandle, compat_data)->value;
209
210 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
211 aprint_error(": couldn't get registers\n");
212 return;
213 }
214 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
215 aprint_error(": couldn't map registers\n");
216 return;
217 }
218
219 /* Enable clocks */
220 for (n = 0; (clk = fdtbus_clock_get_index(phandle, n)) != NULL; n++)
221 if (clk_enable(clk) != 0) {
222 aprint_error(": couldn't enable clock #%d\n", n);
223 return;
224 }
225 /* De-assert resets */
226 for (n = 0; (rst = fdtbus_reset_get_index(phandle, n)) != NULL; n++)
227 if (fdtbus_reset_deassert(rst) != 0) {
228 aprint_error(": couldn't de-assert reset #%d\n", n);
229 return;
230 }
231
232 sc->sc_dr_mode = meson_usbphy_dr_mode(sc);
233
234 aprint_naive("\n");
235 aprint_normal(": USB2 PHY (%s)\n", sc->sc_dr_mode ? sc->sc_dr_mode : "unknown mode");
236
237 fdtbus_register_phy_controller(self, phandle, &meson_usbphy_funcs);
238 }
239