xref: /netbsd-src/sys/arch/arm/amlogic/meson_usbctrl.c (revision 90313c06e62e910bf0d1bb24faa9d17dcefd0ab6)
1 /* $NetBSD: meson_usbctrl.c,v 1.6 2024/02/07 04:20:26 msaitoh Exp $ */
2 
3 /*
4  * Copyright (c) 2021 Ryo Shimizu
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
17  * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
20  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
24  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
25  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26  * POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: meson_usbctrl.c,v 1.6 2024/02/07 04:20:26 msaitoh Exp $");
31 
32 #include <sys/param.h>
33 #include <sys/types.h>
34 #include <sys/bus.h>
35 #include <sys/device.h>
36 
37 #include <dev/fdt/fdtvar.h>
38 
39 /*
40  * USB Glue registers: 0xffe09000
41  */
42 
43 /* usb2 phy ports control registers */
44 #define MESONUSBCTRL_MAXPHYS				3
45 #define U2P_R0_REG(i)					(0x20 * (i) + 0x00)
46 #define  U2P_R0_DRV_VBUS				__BIT(5)
47 #define  U2P_R0_ID_PULLUP				__BIT(4)
48 #define  U2P_R0_POWER_ON_RESET				__BIT(3)
49 #define  U2P_R0_HAST_MODE				__BIT(2)
50 #define  U2P_R0_POWER_OK				__BIT(1)
51 #define  U2P_R0_HOST_DEVICE				__BIT(0)
52 #define U2P_R1_REG(i)					(0x20 * (i) + 0x04)
53 #define  U2P_R1_VBUS_VALID				__BIT(3)
54 #define  U2P_R1_OTG_SESSION_VALID			__BIT(2)
55 #define  U2P_R1_ID_DIG					__BIT(1)
56 #define  U2P_R1_PHY_READY				__BIT(0)
57 
58 /* glue registers */
59 #define USB_R0_REG					0x80
60 #define  USB_R0_U2D_ACT					__BIT(31)
61 #define  USB_R0_U2D_SS_SCALEDOWN_MODE_MASK		__BITS(30,29)
62 #define  USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK		__BITS(28,19)
63 #define  USB_R0_P30_LANE0_EXT_PCLK_REQ			__BIT(18)
64 #define  USB_R0_P30_LANE0_TX2RX_LOOPBACK		__BIT(17)
65 #define USB_R1_REG					0x84
66 #define  USB_R1_P30_PCS_TX_SWING_FULL_MASK		__BITS(31,25)
67 #define  USB_R1_U3H_FLADJ_30MHZ_REG_MASK		__BITS(24,19)
68 #define  USB_R1_U3H_HOST_MSI_ENABLE			__BIT(18)
69 #define  USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT	__BIT(17)
70 #define  USB_R1_U3H_HOST_U3_PORT_DISABLE		__BIT(16)
71 #define  USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK		__BITS(13,12)
72 #define  USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK		__BITS(9,7)
73 #define  USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK		__BITS(4,2)
74 #define  USB_R1_U3H_PME_ENABLE				__BIT(1)
75 #define  USB_R1_U3H_BIGENDIAN_GS			__BIT(0)
76 #define USB_R2_REG					0x88
77 #define  USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK		__BITS(31,26)
78 #define  USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK		__BITS(25,20)
79 #define USB_R3_REG					0x8c
80 #define  USB_R3_P30_REF_SSP_EN				__BIT(13)
81 #define  USB_R3_P30_SSC_REF_CLK_SEL_MASK		__BITS(12,4)
82 #define  USB_R3_P30_SSC_RANGE_MASK			__BITS(3,1)
83 #define  USB_R3_P30_SSC_ENABLE				__BIT(0)
84 #define USB_R4_REG					0x90
85 #define  USB_R4_P21_ONLY				__BIT(4)
86 #define  USB_R4_MEM_PD_MASK				__BITS(3,2)
87 #define  USB_R4_P21_SLEEP_M0				__BIT(1)
88 #define  USB_R4_P21_PORT_RESET_0			__BIT(0)
89 #define USB_R5_REG					0x94
90 #define  USB_R5_ID_DIG_CNT_MASK				__BITS(23,16)
91 #define  USB_R5_ID_DIG_TH_MASK				__BITS(15,8)
92 #define  USB_R5_ID_DIG_IRQ				__BIT(7)
93 #define  USB_R5_ID_DIG_CURR				__BIT(6)
94 #define  USB_R5_ID_DIG_EN_1				__BIT(5)
95 #define  USB_R5_ID_DIG_EN_0				__BIT(4)
96 #define  USB_R5_ID_DIG_CFG_MASK				__BITS(3,2)
97 #define  USB_R5_ID_DIG_REG				__BIT(1)
98 #define  USB_R5_ID_DIG_SYNC				__BIT(0)
99 
100 #define USBCTRL_READ_REG(sc, reg) \
101 	bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
102 #define USBCTRL_WRITE_REG(sc, reg, val) \
103 	bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
104 
105 struct meson_usbctrl_config {
106 	int num_phys;
107 };
108 
109 struct meson_usbctrl_config mesong12_conf = {
110 	.num_phys = 3
111 };
112 
113 static const struct device_compatible_entry compat_data[] = {
114 	{ .compat = "amlogic,meson-g12a-usb-ctrl", .data = &mesong12_conf },
115 	DEVICE_COMPAT_EOL
116 };
117 
118 struct meson_usbctrl_softc {
119 	device_t sc_dev;
120 	bus_space_tag_t sc_bst;
121 	bus_space_handle_t sc_bsh;
122 	const struct meson_usbctrl_config *sc_conf;
123 	struct fdtbus_regulator *sc_supply;
124 	int sc_phandle;
125 };
126 
127 static void
meson_usbctrl_usb2_init(struct meson_usbctrl_softc * sc)128 meson_usbctrl_usb2_init(struct meson_usbctrl_softc *sc)
129 {
130 	int i;
131 	const char *p;
132 
133 	for (i = 0; i < sc->sc_conf->num_phys; i++) {
134 		/* setup only for usb2 phys */
135 		p = fdtbus_get_string_index(sc->sc_phandle, "phy-names", i);
136 		if (p == NULL || strstr(p, "usb2") == NULL)
137 			continue;
138 
139 		USBCTRL_WRITE_REG(sc, U2P_R0_REG(i),
140 		    USBCTRL_READ_REG(sc, U2P_R0_REG(i)) |
141 		    U2P_R0_POWER_ON_RESET);
142 
143 		/* XXX: OTG not supported. always set HOST_DEVICE mode */
144 		USBCTRL_WRITE_REG(sc, U2P_R0_REG(i),
145 		    USBCTRL_READ_REG(sc, U2P_R0_REG(i)) |
146 		    U2P_R0_HOST_DEVICE);
147 
148 		USBCTRL_WRITE_REG(sc, U2P_R0_REG(i),
149 		    USBCTRL_READ_REG(sc, U2P_R0_REG(i)) &
150 		    ~U2P_R0_POWER_ON_RESET);
151 	}
152 }
153 
154 static void
meson_usbctrl_usb_glue_init(struct meson_usbctrl_softc * sc)155 meson_usbctrl_usb_glue_init(struct meson_usbctrl_softc *sc)
156 {
157 	uint32_t val;
158 
159 	val = USBCTRL_READ_REG(sc, USB_R1_REG);
160 	val &= ~USB_R1_U3H_FLADJ_30MHZ_REG_MASK;
161 	val |= __SHIFTIN(0x20, USB_R1_U3H_FLADJ_30MHZ_REG_MASK);
162 	USBCTRL_WRITE_REG(sc, USB_R1_REG, val);
163 
164 	val = USBCTRL_READ_REG(sc, USB_R5_REG);
165 	val |= USB_R5_ID_DIG_EN_0;
166 	USBCTRL_WRITE_REG(sc, USB_R5_REG, val);
167 
168 	val = USBCTRL_READ_REG(sc, USB_R5_REG);
169 	val |= USB_R5_ID_DIG_EN_1;
170 	USBCTRL_WRITE_REG(sc, USB_R5_REG, val);
171 
172 	val = USBCTRL_READ_REG(sc, USB_R5_REG);
173 	val &= ~USB_R5_ID_DIG_TH_MASK;
174 	val |= __SHIFTIN(0xff, USB_R5_ID_DIG_TH_MASK);
175 	USBCTRL_WRITE_REG(sc, USB_R5_REG, val);
176 }
177 
178 static void
meson_usbctrl_usb3_init(struct meson_usbctrl_softc * sc)179 meson_usbctrl_usb3_init(struct meson_usbctrl_softc *sc)
180 {
181 	uint32_t val;
182 
183 	val = USBCTRL_READ_REG(sc, USB_R3_REG);
184 	val &= ~USB_R3_P30_SSC_RANGE_MASK;
185 	val &= ~USB_R3_P30_SSC_ENABLE;
186 	val |= __SHIFTIN(2, USB_R3_P30_SSC_RANGE_MASK);
187 	val |= USB_R3_P30_REF_SSP_EN;
188 	USBCTRL_WRITE_REG(sc, USB_R3_REG, val);
189 
190 	delay(2);
191 
192 	val = USBCTRL_READ_REG(sc, USB_R2_REG);
193 	val &= ~USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK;
194 	val |= __SHIFTIN(0x15, USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK);
195 	USBCTRL_WRITE_REG(sc, USB_R2_REG, val);
196 
197 	val = USBCTRL_READ_REG(sc, USB_R2_REG);
198 	val &= ~USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK;
199 	val |= __SHIFTIN(0x20, USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK);
200 	USBCTRL_WRITE_REG(sc, USB_R2_REG, val);
201 
202 	delay(2);
203 
204 	val = USBCTRL_READ_REG(sc, USB_R1_REG);
205 	val |= USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT;
206 	USBCTRL_WRITE_REG(sc, USB_R1_REG, val);
207 
208 	val = USBCTRL_READ_REG(sc, USB_R1_REG);
209 	val &= ~USB_R1_P30_PCS_TX_SWING_FULL_MASK;
210 	val |= __SHIFTIN(127, USB_R1_P30_PCS_TX_SWING_FULL_MASK);
211 	USBCTRL_WRITE_REG(sc, USB_R1_REG, val);
212 
213 	/* XXX: force HOST_DEVICE mode */
214 	val = USBCTRL_READ_REG(sc, USB_R0_REG);
215 	val &= ~USB_R0_U2D_ACT;
216 	USBCTRL_WRITE_REG(sc, USB_R0_REG, val);
217 
218 	val = USBCTRL_READ_REG(sc, USB_R4_REG);
219 	val &= ~USB_R4_P21_SLEEP_M0;
220 	USBCTRL_WRITE_REG(sc, USB_R4_REG, val);
221 }
222 
223 static void
meson_usbctrl_enable_usb3_phys(struct meson_usbctrl_softc * sc)224 meson_usbctrl_enable_usb3_phys(struct meson_usbctrl_softc *sc)
225 {
226 	struct fdtbus_phy *phy;
227 	int i;
228 	const char *phyname;
229 
230 	/*
231 	 * enable only for usb3 phys.
232 	 * node of "snps,dwc3" decl in "amlogic,meson-g12a-usb-ctrl" have
233 	 * no "phys" property, so enable the phy here.
234 	 */
235 	for (i = 0; i < sc->sc_conf->num_phys; i++) {
236 		phyname = fdtbus_get_string_index(sc->sc_phandle,
237 		    "phy-names", i);
238 		if (strstr(phyname, "usb3") == NULL)
239 			continue;
240 
241 		phy = fdtbus_phy_get_index(sc->sc_phandle, i);
242 		if (phy == NULL)
243 			continue;
244 		if (fdtbus_phy_enable(phy, true) != 0)
245 			aprint_error_dev(sc->sc_dev, "couldn't enable phy %s\n",
246 			    phyname);
247 	}
248 }
249 
250 static int
meson_usbctrl_match(device_t parent,cfdata_t cf,void * aux)251 meson_usbctrl_match(device_t parent, cfdata_t cf, void *aux)
252 {
253 	struct fdt_attach_args * const faa = aux;
254 
255 	return of_compatible_match(faa->faa_phandle, compat_data);
256 }
257 
258 static void
meson_usbctrl_attach(device_t parent,device_t self,void * aux)259 meson_usbctrl_attach(device_t parent, device_t self, void *aux)
260 {
261 	struct meson_usbctrl_softc * const sc = device_private(self);
262 	struct fdt_attach_args * const faa = aux;
263 	bus_addr_t addr;
264 	bus_size_t size;
265 	int phandle, child;
266 
267 	sc->sc_dev = self;
268 	sc->sc_bst = faa->faa_bst;
269 	sc->sc_phandle = phandle = faa->faa_phandle;
270 	sc->sc_conf = of_compatible_lookup(phandle, compat_data)->data;
271 
272 	if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
273 		aprint_error(": couldn't get registers\n");
274 		return;
275 	}
276 	if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
277 		aprint_error(": couldn't map registers\n");
278 		return;
279 	}
280 
281 	aprint_naive("\n");
282 	aprint_normal(": USB Controllers\n");
283 
284 	sc->sc_supply = fdtbus_regulator_acquire(phandle, "vbus-supply");
285 	if (sc->sc_supply != NULL)
286 		fdtbus_regulator_enable(sc->sc_supply);	/* USB HOST MODE */
287 
288 	meson_usbctrl_usb2_init(sc);
289 	meson_usbctrl_usb_glue_init(sc);
290 	meson_usbctrl_usb3_init(sc);
291 	meson_usbctrl_enable_usb3_phys(sc);
292 
293 	for (child = OF_child(phandle); child; child = OF_peer(child)) {
294 		fdt_add_child(parent, child, faa, 0);
295 	}
296 }
297 
298 CFATTACH_DECL_NEW(meson_usbctrl, sizeof(struct meson_usbctrl_softc),
299     meson_usbctrl_match, meson_usbctrl_attach, NULL, NULL);
300