1 /* $NetBSD: meson_clk_pll.c,v 1.3 2021/01/01 07:21:58 ryo Exp $ */
2
3 /*-
4 * Copyright (c) 2019 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: meson_clk_pll.c,v 1.3 2021/01/01 07:21:58 ryo Exp $");
31
32 #include <sys/param.h>
33 #include <sys/bus.h>
34
35 #include <dev/clk/clk_backend.h>
36
37 #include <arm/amlogic/meson_clk.h>
38
39 u_int
meson_clk_pll_get_rate(struct meson_clk_softc * sc,struct meson_clk_clk * clk)40 meson_clk_pll_get_rate(struct meson_clk_softc *sc,
41 struct meson_clk_clk *clk)
42 {
43 struct meson_clk_pll *pll = &clk->u.pll;
44 struct clk *clkp, *clkp_parent;
45 u_int n, m, frac;
46 uint64_t parent_rate, rate;
47 uint32_t val;
48
49 KASSERT(clk->type == MESON_CLK_PLL);
50
51 clkp = &clk->base;
52 clkp_parent = clk_get_parent(clkp);
53 if (clkp_parent == NULL)
54 return 0;
55
56 parent_rate = clk_get_rate(clkp_parent);
57 if (parent_rate == 0)
58 return 0;
59
60 CLK_LOCK(sc);
61
62 val = CLK_READ(sc, pll->n.reg);
63 n = __SHIFTOUT(val, pll->n.mask);
64
65 val = CLK_READ(sc, pll->m.reg);
66 m = __SHIFTOUT(val, pll->m.mask);
67
68 if (pll->frac.mask) {
69 val = CLK_READ(sc, pll->frac.reg);
70 frac = __SHIFTOUT(val, pll->frac.mask);
71 } else {
72 frac = 0;
73 }
74
75 CLK_UNLOCK(sc);
76
77 rate = parent_rate * m;
78 if (frac) {
79 uint64_t frac_rate = parent_rate * frac;
80 rate += howmany(frac_rate, __SHIFTOUT_MASK(pll->frac.mask) + 1);
81 }
82
83 return (u_int)howmany(rate, n);
84 }
85
86 /* the lock must have been acquired with CLK_LOCK() */
87 int
meson_clk_pll_wait_lock(struct meson_clk_softc * sc,struct meson_clk_pll * pll)88 meson_clk_pll_wait_lock(struct meson_clk_softc *sc, struct meson_clk_pll *pll)
89 {
90 int i;
91 for (i = 24000000; i > 0; i--) {
92 if ((CLK_READ(sc, pll->l.reg) & pll->l.mask) != 0)
93 return 0;
94 }
95 return ETIMEDOUT;
96 }
97
98 int
meson_clk_pll_set_rate(struct meson_clk_softc * sc,struct meson_clk_clk * clk,u_int new_rate)99 meson_clk_pll_set_rate(struct meson_clk_softc *sc, struct meson_clk_clk *clk,
100 u_int new_rate)
101 {
102 struct meson_clk_pll *pll = &clk->u.pll;
103 struct clk *clkp, *clkp_parent;
104 uint64_t parent_rate, tmp;
105 uint32_t n, m, m_max, frac, frac_max;
106 int error;
107
108 KASSERT(clk->type == MESON_CLK_PLL);
109
110 clkp = &clk->base;
111 clkp_parent = clk_get_parent(clkp);
112 if (clkp_parent == NULL)
113 return ENXIO;
114
115 if ((pll->flags & MESON_CLK_DIV_SET_RATE_PARENT) != 0)
116 return clk_set_rate(clkp_parent, new_rate);
117
118 parent_rate = clk_get_rate(clkp_parent);
119 if (parent_rate == 0) {
120 error = (new_rate == 0) ? 0 : ERANGE;
121 return error;
122 }
123
124 if (parent_rate > new_rate) {
125 n = parent_rate / new_rate;
126 parent_rate /= n;
127 } else {
128 n = 1;
129 }
130
131 #define DIV_ROUND_OFF(x, y) (((x) + (y) / 2) / (y))
132 m_max = __SHIFTOUT(pll->m.mask, pll->m.mask);
133 frac_max = __SHIFTOUT(pll->frac.mask, pll->frac.mask);
134 tmp = DIV_ROUND_OFF(new_rate * (frac_max + 1), parent_rate);
135 m = tmp / (frac_max + 1);
136 frac = tmp & frac_max;
137
138 if (m > m_max)
139 return ERANGE;
140
141 CLK_LOCK(sc);
142
143 /* reset */
144 CLK_WRITE_BITS(sc, pll->reset.reg, pll->reset.mask, 1);
145 CLK_WRITE_BITS(sc, pll->reset.reg, pll->reset.mask, 0);
146 error = meson_clk_pll_wait_lock(sc, pll);
147 if (error != 0)
148 goto failure;
149
150 /* disable */
151 CLK_WRITE_BITS(sc, pll->reset.reg, pll->reset.mask, 1);
152 CLK_WRITE_BITS(sc, pll->enable.reg, pll->enable.mask, 0);
153
154 /* write new M, N, and FRAC */
155 CLK_WRITE_BITS(sc, pll->m.reg, pll->m.mask, m);
156 CLK_WRITE_BITS(sc, pll->n.reg, pll->n.mask, n);
157 if (pll->frac.mask) {
158 CLK_WRITE_BITS(sc, pll->frac.reg, pll->frac.mask, frac);
159 }
160
161 /* enable */
162 CLK_WRITE_BITS(sc, pll->reset.reg, pll->reset.mask, 1);
163 CLK_WRITE_BITS(sc, pll->enable.reg, pll->enable.mask, 1);
164 DELAY(1000);
165 CLK_WRITE_BITS(sc, pll->reset.reg, pll->reset.mask, 0);
166 error = meson_clk_pll_wait_lock(sc, pll);
167 failure:
168 CLK_UNLOCK(sc);
169
170 return error;
171 }
172
173 const char *
meson_clk_pll_get_parent(struct meson_clk_softc * sc,struct meson_clk_clk * clk)174 meson_clk_pll_get_parent(struct meson_clk_softc *sc,
175 struct meson_clk_clk *clk)
176 {
177 struct meson_clk_pll *pll = &clk->u.pll;
178
179 KASSERT(clk->type == MESON_CLK_PLL);
180
181 return pll->parent;
182 }
183