1 /* $NetBSD: meson8b_clkc.c,v 1.6 2021/01/27 03:10:18 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2019 Jared McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30
31 __KERNEL_RCSID(1, "$NetBSD: meson8b_clkc.c,v 1.6 2021/01/27 03:10:18 thorpej Exp $");
32
33 #include <sys/param.h>
34 #include <sys/bus.h>
35 #include <sys/device.h>
36 #include <sys/systm.h>
37
38 #include <dev/fdt/fdtvar.h>
39
40 #include <arm/amlogic/meson_clk.h>
41 #include <arm/amlogic/meson8b_clkc.h>
42
43 /*
44 * The DT for amlogic,meson8b-clkc defines two reg resources. The first
45 * is not used by this driver.
46 */
47 #define MESON8B_CLKC_REG_INDEX 1
48
49 #define CBUS_REG(x) ((x) << 2)
50
51 #define HHI_GCLK_MPEG0 CBUS_REG(0x50)
52 #define HHI_GCLK_MPEG1 CBUS_REG(0x51)
53 #define HHI_GCLK_MPEG2 CBUS_REG(0x52)
54 #define HHI_SYS_CPU_CLK_CNTL1 CBUS_REG(0x57)
55 #define HHI_MPEG_CLK_CNTL CBUS_REG(0x5d)
56 #define HHI_SYS_CPU_CLK_CNTL0 CBUS_REG(0x67)
57 #define HHI_SYS_CPU_CLK_CNTL0_CLKSEL __BIT(7)
58 #define HHI_SYS_CPU_CLK_CNTL0_SOUTSEL __BITS(3,2)
59 #define HHI_SYS_CPU_CLK_CNTL0_PLLSEL __BITS(1,0)
60 #define HHI_MPLL_CNTL CBUS_REG(0xa0)
61 #define HHI_MPLL_CNTL2 CBUS_REG(0xa1)
62 #define HHI_MPLL_CNTL5 CBUS_REG(0xa4)
63 #define HHI_MPLL_CNTL6 CBUS_REG(0xa5)
64 #define HHI_MPLL_CNTL7 CBUS_REG(0xa6)
65 #define HHI_MPLL_CNTL8 CBUS_REG(0xa7)
66 #define HHI_MPLL_CNTL9 CBUS_REG(0xa8)
67 #define HHI_SYS_PLL_CNTL CBUS_REG(0xc0)
68 #define HHI_SYS_PLL_CNTL_LOCK __BIT(31)
69 #define HHI_SYS_PLL_CNTL_OD __BITS(17,16)
70 #define HHI_SYS_PLL_CNTL_DIV __BITS(14,9)
71 #define HHI_SYS_PLL_CNTL_MUL __BITS(8,0)
72
73 static int meson8b_clkc_match(device_t, cfdata_t, void *);
74 static void meson8b_clkc_attach(device_t, device_t, void *);
75
76 static const struct device_compatible_entry compat_data[] = {
77 { .compat = "amlogic,meson8-clkc" },
78 { .compat = "amlogic,meson8b-clkc" },
79 DEVICE_COMPAT_EOL
80 };
81
82 CFATTACH_DECL_NEW(meson8b_clkc, sizeof(struct meson_clk_softc),
83 meson8b_clkc_match, meson8b_clkc_attach, NULL, NULL);
84
85 static struct meson_clk_reset meson8b_clkc_resets[] = {
86 MESON_CLK_RESET(MESON8B_RESET_CPU0_SOFT_RESET, HHI_SYS_CPU_CLK_CNTL0, 24),
87 MESON_CLK_RESET(MESON8B_RESET_CPU1_SOFT_RESET, HHI_SYS_CPU_CLK_CNTL0, 25),
88 MESON_CLK_RESET(MESON8B_RESET_CPU2_SOFT_RESET, HHI_SYS_CPU_CLK_CNTL0, 26),
89 MESON_CLK_RESET(MESON8B_RESET_CPU3_SOFT_RESET, HHI_SYS_CPU_CLK_CNTL0, 27),
90 };
91
92 static const char *mpeg_sel_parents[] = { "xtal", NULL, "fclk_div7", "mpll_clkout1", "mpll_clkout2", "fclk_div4", "fclk_div3", "fclk_div5" };
93 static const char *cpu_in_sel_parents[] = { "xtal", "sys_pll" };
94 static const char *cpu_scale_out_sel_parents[] = { "cpu_in_sel", "cpu_in_div2", "cpu_in_div3", "cpu_scale_div" };
95 static const char *cpu_clk_parents[] = { "xtal", "cpu_scale_out_sel" };
96 static const char *periph_clk_sel_parents[] = { "cpu_clk_div2", "cpu_clk_div3", "cpu_clk_div4", "cpu_clk_div5", "cpu_clk_div6", "cpu_clk_div7", "cpu_clk_div8" };
97
98 static int
meson8b_clkc_pll_sys_set_rate(struct meson_clk_softc * sc,struct meson_clk_clk * clk,u_int rate)99 meson8b_clkc_pll_sys_set_rate(struct meson_clk_softc *sc,
100 struct meson_clk_clk *clk, u_int rate)
101 {
102 struct clk *clkp, *clkp_parent;
103 int error;
104
105 KASSERT(clk->type == MESON_CLK_PLL);
106
107 clkp = &clk->base;
108 clkp_parent = clk_get_parent(clkp);
109 if (clkp_parent == NULL)
110 return ENXIO;
111
112 const u_int old_rate = clk_get_rate(clkp);
113 if (old_rate == rate)
114 return 0;
115
116 const u_int parent_rate = clk_get_rate(clkp_parent);
117 if (parent_rate == 0)
118 return EIO;
119
120 CLK_LOCK(sc);
121
122 uint32_t cntl0 = CLK_READ(sc, HHI_SYS_CPU_CLK_CNTL0);
123 uint32_t cntl = CLK_READ(sc, HHI_SYS_PLL_CNTL);
124
125 u_int new_mul = rate / parent_rate;
126 u_int new_div = 1;
127 u_int new_od = 0;
128
129 if (rate < 600 * 1000000) {
130 new_od = 2;
131 new_mul *= 4;
132 } else if (rate < 1200 * 1000000) {
133 new_od = 1;
134 new_mul *= 2;
135 }
136
137 if ((cntl0 & HHI_SYS_CPU_CLK_CNTL0_CLKSEL) == 0) {
138 error = EIO;
139 goto done;
140 }
141 if (__SHIFTOUT(cntl0, HHI_SYS_CPU_CLK_CNTL0_PLLSEL) != 1) {
142 error = EIO;
143 goto done;
144 }
145 if (__SHIFTOUT(cntl0, HHI_SYS_CPU_CLK_CNTL0_SOUTSEL) != 0) {
146 error = EIO;
147 goto done;
148 }
149
150 cntl &= ~HHI_SYS_PLL_CNTL_MUL;
151 cntl |= __SHIFTIN(new_mul, HHI_SYS_PLL_CNTL_MUL);
152 cntl &= ~HHI_SYS_PLL_CNTL_DIV;
153 cntl |= __SHIFTIN(new_div, HHI_SYS_PLL_CNTL_DIV);
154 cntl &= ~HHI_SYS_PLL_CNTL_OD;
155 cntl |= __SHIFTIN(new_od, HHI_SYS_PLL_CNTL_OD);
156
157 /* Switch CPU to XTAL clock */
158 cntl0 &= ~HHI_SYS_CPU_CLK_CNTL0_CLKSEL;
159 CLK_WRITE(sc, HHI_SYS_CPU_CLK_CNTL0, cntl0);
160
161 delay((100 * old_rate) / parent_rate);
162
163 /* Update multiplier */
164 do {
165 CLK_WRITE(sc, HHI_SYS_PLL_CNTL, cntl);
166
167 /* Switch CPU to sys pll */
168 cntl0 |= HHI_SYS_CPU_CLK_CNTL0_CLKSEL;
169 CLK_WRITE(sc, HHI_SYS_CPU_CLK_CNTL0, cntl0);
170 } while ((CLK_READ(sc, HHI_SYS_PLL_CNTL) & HHI_SYS_PLL_CNTL_LOCK) == 0);
171
172 error = 0;
173
174 done:
175 CLK_UNLOCK(sc);
176
177 return error;
178 }
179
180 static struct meson_clk_clk meson8b_clkc_clks[] = {
181
182 MESON_CLK_FIXED(MESON8B_CLOCK_XTAL, "xtal", 24000000),
183
184 MESON_CLK_PLL_RATE(MESON8B_CLOCK_PLL_SYS_DCO, "pll_sys_dco", "xtal",
185 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(30)), /* enable */
186 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BITS(8,0)), /* m */
187 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BITS(13,9)), /* n */
188 MESON_CLK_PLL_REG_INVALID, /* frac */
189 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(31)), /* l */
190 MESON_CLK_PLL_REG(HHI_SYS_PLL_CNTL, __BIT(29)), /* reset */
191 meson8b_clkc_pll_sys_set_rate,
192 0),
193
194 MESON_CLK_DIV(MESON8B_CLOCK_PLL_SYS, "sys_pll", "pll_sys_dco",
195 HHI_SYS_PLL_CNTL, /* reg */
196 __BITS(17,16), /* div */
197 MESON_CLK_DIV_POWER_OF_TWO | MESON_CLK_DIV_SET_RATE_PARENT),
198
199 MESON_CLK_MUX(MESON8B_CLOCK_CPU_IN_SEL, "cpu_in_sel", cpu_in_sel_parents,
200 HHI_SYS_CPU_CLK_CNTL0, /* reg */
201 __BIT(0), /* sel */
202 0),
203
204 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_IN_DIV2, "cpu_in_div2", "cpu_in_sel", 2, 1),
205 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_IN_DIV3, "cpu_in_div3", "cpu_in_sel", 3, 1),
206
207 MESON_CLK_DIV(MESON8B_CLOCK_CPU_SCALE_DIV, "cpu_scale_div", "cpu_in_sel",
208 HHI_SYS_CPU_CLK_CNTL1, /* reg */
209 __BITS(29,20), /* div */
210 MESON_CLK_DIV_CPU_SCALE_TABLE | MESON_CLK_DIV_SET_RATE_PARENT),
211
212 MESON_CLK_MUX(MESON8B_CLOCK_CPU_SCALE_OUT_SEL, "cpu_scale_out_sel", cpu_scale_out_sel_parents,
213 HHI_SYS_CPU_CLK_CNTL0, /* reg */
214 __BITS(3,2), /* sel */
215 0),
216
217 MESON_CLK_MUX(MESON8B_CLOCK_CPUCLK, "cpu_clk", cpu_clk_parents,
218 HHI_SYS_CPU_CLK_CNTL0, /* reg */
219 __BIT(7), /* sel */
220 0),
221
222 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_CLK_DIV2, "cpu_clk_div2", "cpu_clk", 2, 1),
223 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_CLK_DIV3, "cpu_clk_div3", "cpu_clk", 3, 1),
224 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_CLK_DIV4, "cpu_clk_div4", "cpu_clk", 4, 1),
225 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_CLK_DIV5, "cpu_clk_div5", "cpu_clk", 5, 1),
226 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_CLK_DIV6, "cpu_clk_div6", "cpu_clk", 6, 1),
227 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_CLK_DIV7, "cpu_clk_div7", "cpu_clk", 7, 1),
228 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_CPU_CLK_DIV8, "cpu_clk_div8", "cpu_clk", 8, 1),
229
230 MESON_CLK_MUX(MESON8B_CLOCK_PERIPH_SEL, "periph_clk_sel", periph_clk_sel_parents,
231 HHI_SYS_CPU_CLK_CNTL1, /* reg */
232 __BITS(8,6), /* sel */
233 0),
234 MESON_CLK_GATE_FLAGS(MESON8B_CLOCK_PERIPH, "periph_clk_dis", "periph_clk_sel",
235 HHI_SYS_CPU_CLK_CNTL1, /* reg */
236 17, /* bit */
237 MESON_CLK_GATE_SET_TO_DISABLE),
238
239 MESON_CLK_PLL(MESON8B_CLOCK_PLL_FIXED_DCO, "pll_fixed_dco", "xtal",
240 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(30)), /* enable */
241 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BITS(8,0)), /* m */
242 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BITS(13,9)), /* n */
243 MESON_CLK_PLL_REG(HHI_MPLL_CNTL2, __BITS(11,0)), /* frac */
244 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(31)), /* l */
245 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(29)), /* reset */
246 0),
247
248 MESON_CLK_DIV(MESON8B_CLOCK_PLL_FIXED, "pll_fixed", "pll_fixed_dco",
249 HHI_MPLL_CNTL, /* reg */
250 __BITS(17,16), /* div */
251 MESON_CLK_DIV_POWER_OF_TWO),
252
253 MESON_CLK_DIV(MESON8B_CLOCK_MPLL_PREDIV, "mpll_prediv", "pll_fixed",
254 HHI_MPLL_CNTL5, /* reg */
255 __BIT(12), /* div */
256 0),
257
258 MESON_CLK_MPLL(MESON8B_CLOCK_MPLL0_DIV, "mpll0_div", "mpll_prediv",
259 MESON_CLK_PLL_REG(HHI_MPLL_CNTL7, __BITS(13,0)), /* sdm */
260 MESON_CLK_PLL_REG(HHI_MPLL_CNTL7, __BIT(15)), /* sdm_enable */
261 MESON_CLK_PLL_REG(HHI_MPLL_CNTL7, __BITS(24,16)), /* n2 */
262 MESON_CLK_PLL_REG(HHI_MPLL_CNTL, __BIT(25)), /* ssen */
263 0),
264 MESON_CLK_MPLL(MESON8B_CLOCK_MPLL1_DIV, "mpll1_div", "mpll_prediv",
265 MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BITS(13,0)), /* sdm */
266 MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BIT(15)), /* sdm_enable */
267 MESON_CLK_PLL_REG(HHI_MPLL_CNTL8, __BITS(24,16)), /* n2 */
268 MESON_CLK_PLL_REG_INVALID, /* ssen */
269 0),
270 MESON_CLK_MPLL(MESON8B_CLOCK_MPLL2_DIV, "mpll2_div", "mpll_prediv",
271 MESON_CLK_PLL_REG(HHI_MPLL_CNTL9, __BITS(13,0)), /* sdm */
272 MESON_CLK_PLL_REG(HHI_MPLL_CNTL9, __BIT(15)), /* sdm_enable */
273 MESON_CLK_PLL_REG(HHI_MPLL_CNTL9, __BITS(24,16)), /* n2 */
274 MESON_CLK_PLL_REG_INVALID, /* ssen */
275 0),
276
277 MESON_CLK_GATE(MESON8B_CLOCK_MPLL0, "mpll0", "mpll0_div", HHI_MPLL_CNTL7, 14),
278 MESON_CLK_GATE(MESON8B_CLOCK_MPLL1, "mpll1", "mpll1_div", HHI_MPLL_CNTL8, 14),
279 MESON_CLK_GATE(MESON8B_CLOCK_MPLL2, "mpll2", "mpll2_div", HHI_MPLL_CNTL9, 14),
280
281 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_FCLK_DIV2_DIV, "fclk_div2_div", "pll_fixed", 2, 1),
282 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_FCLK_DIV3_DIV, "fclk_div3_div", "pll_fixed", 3, 1),
283 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_FCLK_DIV4_DIV, "fclk_div4_div", "pll_fixed", 4, 1),
284 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_FCLK_DIV5_DIV, "fclk_div5_div", "pll_fixed", 5, 1),
285 MESON_CLK_FIXED_FACTOR(MESON8B_CLOCK_FCLK_DIV7_DIV, "fclk_div7_div", "pll_fixed", 7, 1),
286
287 MESON_CLK_GATE(MESON8B_CLOCK_FCLK_DIV2, "fclk_div2", "fclk_div2_div", HHI_MPLL_CNTL6, 27),
288 MESON_CLK_GATE(MESON8B_CLOCK_FCLK_DIV3, "fclk_div3", "fclk_div3_div", HHI_MPLL_CNTL6, 28),
289 MESON_CLK_GATE(MESON8B_CLOCK_FCLK_DIV4, "fclk_div4", "fclk_div4_div", HHI_MPLL_CNTL6, 29),
290 MESON_CLK_GATE(MESON8B_CLOCK_FCLK_DIV5, "fclk_div5", "fclk_div5_div", HHI_MPLL_CNTL6, 30),
291 MESON_CLK_GATE(MESON8B_CLOCK_FCLK_DIV7, "fclk_div7", "fclk_div7_div", HHI_MPLL_CNTL6, 31),
292
293 MESON_CLK_MUX(MESON8B_CLOCK_MPEG_SEL, "mpeg_sel", mpeg_sel_parents,
294 HHI_MPEG_CLK_CNTL, /* reg */
295 __BITS(14,12), /* sel */
296 0),
297
298 MESON_CLK_DIV(MESON8B_CLOCK_MPEG_DIV, "mpeg_div", "mpeg_sel",
299 HHI_MPEG_CLK_CNTL, /* reg */
300 __BITS(6,0), /* div */
301 0),
302
303 MESON_CLK_GATE(MESON8B_CLOCK_CLK81, "clk81", "mpeg_div", HHI_MPEG_CLK_CNTL, 7),
304
305 MESON_CLK_GATE(MESON8B_CLOCK_I2C, "i2c", "clk81", HHI_GCLK_MPEG0, 9),
306 MESON_CLK_GATE(MESON8B_CLOCK_SAR_ADC, "sar_adc", "clk81", HHI_GCLK_MPEG0, 10),
307 MESON_CLK_GATE(MESON8B_CLOCK_RNG0, "rng0", "clk81", HHI_GCLK_MPEG0, 12),
308 MESON_CLK_GATE(MESON8B_CLOCK_UART0, "uart0", "clk81", HHI_GCLK_MPEG0, 13),
309 MESON_CLK_GATE(MESON8B_CLOCK_SDHC, "sdhc", "clk81", HHI_GCLK_MPEG0, 14),
310 MESON_CLK_GATE(MESON8B_CLOCK_SDIO, "sdio", "clk81", HHI_GCLK_MPEG0, 17),
311
312 MESON_CLK_GATE(MESON8B_CLOCK_ETH, "eth", "clk81", HHI_GCLK_MPEG1, 3),
313 MESON_CLK_GATE(MESON8B_CLOCK_UART1, "uart1", "clk81", HHI_GCLK_MPEG1, 16),
314 MESON_CLK_GATE(MESON8B_CLOCK_USB0, "usb0", "clk81", HHI_GCLK_MPEG1, 21),
315 MESON_CLK_GATE(MESON8B_CLOCK_USB1, "usb1", "clk81", HHI_GCLK_MPEG1, 22),
316 MESON_CLK_GATE(MESON8B_CLOCK_USB, "usb", "clk81", HHI_GCLK_MPEG1, 26),
317 MESON_CLK_GATE(MESON8B_CLOCK_EFUSE, "efuse", "clk81", HHI_GCLK_MPEG1, 30),
318
319 MESON_CLK_GATE(MESON8B_CLOCK_USB1_DDR_BRIDGE, "usb1_ddr_bridge", "clk81", HHI_GCLK_MPEG2, 8),
320 MESON_CLK_GATE(MESON8B_CLOCK_USB0_DDR_BRIDGE, "usb0_ddr_bridge", "clk81", HHI_GCLK_MPEG2, 9),
321 MESON_CLK_GATE(MESON8B_CLOCK_UART2, "uart2", "clk81", HHI_GCLK_MPEG2, 15),
322 };
323
324 static int
meson8b_clkc_match(device_t parent,cfdata_t cf,void * aux)325 meson8b_clkc_match(device_t parent, cfdata_t cf, void *aux)
326 {
327 struct fdt_attach_args * const faa = aux;
328
329 return of_compatible_match(faa->faa_phandle, compat_data);
330 }
331
332 static void
meson8b_clkc_attach(device_t parent,device_t self,void * aux)333 meson8b_clkc_attach(device_t parent, device_t self, void *aux)
334 {
335 struct meson_clk_softc * const sc = device_private(self);
336 struct fdt_attach_args * const faa = aux;
337
338 sc->sc_dev = self;
339 sc->sc_phandle = faa->faa_phandle;
340 sc->sc_syscon = fdtbus_syscon_lookup(OF_parent(sc->sc_phandle));
341 if (sc->sc_syscon == NULL) {
342 aprint_error(": couldn't get syscon registers\n");
343 return;
344 }
345
346 sc->sc_resets = meson8b_clkc_resets;
347 sc->sc_nresets = __arraycount(meson8b_clkc_resets);
348
349 sc->sc_clks = meson8b_clkc_clks;
350 sc->sc_nclks = __arraycount(meson8b_clkc_clks);
351
352 meson_clk_attach(sc);
353
354 aprint_naive("\n");
355 aprint_normal(": Meson8b clock controller\n");
356
357 meson_clk_print(sc);
358 }
359