1 //===--------------------- InstructionInfoView.cpp --------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 ///
10 /// This file implements the InstructionInfoView API.
11 ///
12 //===----------------------------------------------------------------------===//
13
14 #include "Views/InstructionInfoView.h"
15 #include "llvm/Support/FormattedStream.h"
16 #include "llvm/Support/JSON.h"
17
18 namespace llvm {
19 namespace mca {
20
printView(raw_ostream & OS) const21 void InstructionInfoView::printView(raw_ostream &OS) const {
22 std::string Buffer;
23 raw_string_ostream TempStream(Buffer);
24
25 ArrayRef<llvm::MCInst> Source = getSource();
26 if (!Source.size())
27 return;
28
29 IIVDVec IIVD(Source.size());
30 collectData(IIVD);
31
32 TempStream << "\n\nInstruction Info:\n";
33 TempStream << "[1]: #uOps\n[2]: Latency\n[3]: RThroughput\n"
34 << "[4]: MayLoad\n[5]: MayStore\n[6]: HasSideEffects (U)\n";
35 if (PrintBarriers) {
36 TempStream << "[7]: LoadBarrier\n[8]: StoreBarrier\n";
37 }
38 if (PrintEncodings) {
39 if (PrintBarriers) {
40 TempStream << "[9]: Encoding Size\n";
41 TempStream << "\n[1] [2] [3] [4] [5] [6] [7] [8] "
42 << "[9] Encodings: Instructions:\n";
43 } else {
44 TempStream << "[7]: Encoding Size\n";
45 TempStream << "\n[1] [2] [3] [4] [5] [6] [7] "
46 << "Encodings: Instructions:\n";
47 }
48 } else {
49 if (PrintBarriers) {
50 TempStream << "\n[1] [2] [3] [4] [5] [6] [7] [8] "
51 << "Instructions:\n";
52 } else {
53 TempStream << "\n[1] [2] [3] [4] [5] [6] "
54 << "Instructions:\n";
55 }
56 }
57
58 int Index = 0;
59 for (const auto &I : enumerate(zip(IIVD, Source))) {
60 const InstructionInfoViewData &IIVDEntry = std::get<0>(I.value());
61
62 TempStream << ' ' << IIVDEntry.NumMicroOpcodes << " ";
63 if (IIVDEntry.NumMicroOpcodes < 10)
64 TempStream << " ";
65 else if (IIVDEntry.NumMicroOpcodes < 100)
66 TempStream << ' ';
67 TempStream << IIVDEntry.Latency << " ";
68 if (IIVDEntry.Latency < 10)
69 TempStream << " ";
70 else if (IIVDEntry.Latency < 100)
71 TempStream << ' ';
72
73 if (IIVDEntry.RThroughput) {
74 double RT = *IIVDEntry.RThroughput;
75 TempStream << format("%.2f", RT) << ' ';
76 if (RT < 10.0)
77 TempStream << " ";
78 else if (RT < 100.0)
79 TempStream << ' ';
80 } else {
81 TempStream << " - ";
82 }
83 TempStream << (IIVDEntry.mayLoad ? " * " : " ");
84 TempStream << (IIVDEntry.mayStore ? " * " : " ");
85 TempStream << (IIVDEntry.hasUnmodeledSideEffects ? " U " : " ");
86
87 if (PrintBarriers) {
88 TempStream << (LoweredInsts[Index]->isALoadBarrier() ? " * "
89 : " ");
90 TempStream << (LoweredInsts[Index]->isAStoreBarrier() ? " * "
91 : " ");
92 }
93
94 if (PrintEncodings) {
95 StringRef Encoding(CE.getEncoding(I.index()));
96 unsigned EncodingSize = Encoding.size();
97 TempStream << " " << EncodingSize
98 << (EncodingSize < 10 ? " " : " ");
99 TempStream.flush();
100 formatted_raw_ostream FOS(TempStream);
101 for (unsigned i = 0, e = Encoding.size(); i != e; ++i)
102 FOS << format("%02x ", (uint8_t)Encoding[i]);
103 FOS.PadToColumn(30);
104 FOS.flush();
105 }
106
107 const MCInst &Inst = std::get<1>(I.value());
108 TempStream << printInstructionString(Inst) << '\n';
109 ++Index;
110 }
111
112 TempStream.flush();
113 OS << Buffer;
114 }
115
collectData(MutableArrayRef<InstructionInfoViewData> IIVD) const116 void InstructionInfoView::collectData(
117 MutableArrayRef<InstructionInfoViewData> IIVD) const {
118 const llvm::MCSubtargetInfo &STI = getSubTargetInfo();
119 const MCSchedModel &SM = STI.getSchedModel();
120 for (const auto I : zip(getSource(), IIVD)) {
121 const MCInst &Inst = std::get<0>(I);
122 InstructionInfoViewData &IIVDEntry = std::get<1>(I);
123 const MCInstrDesc &MCDesc = MCII.get(Inst.getOpcode());
124
125 // Obtain the scheduling class information from the instruction.
126 unsigned SchedClassID = MCDesc.getSchedClass();
127 unsigned CPUID = SM.getProcessorID();
128
129 // Try to solve variant scheduling classes.
130 while (SchedClassID && SM.getSchedClassDesc(SchedClassID)->isVariant())
131 SchedClassID =
132 STI.resolveVariantSchedClass(SchedClassID, &Inst, &MCII, CPUID);
133
134 const MCSchedClassDesc &SCDesc = *SM.getSchedClassDesc(SchedClassID);
135 IIVDEntry.NumMicroOpcodes = SCDesc.NumMicroOps;
136 IIVDEntry.Latency = MCSchedModel::computeInstrLatency(STI, SCDesc);
137 // Add extra latency due to delays in the forwarding data paths.
138 IIVDEntry.Latency += MCSchedModel::getForwardingDelayCycles(
139 STI.getReadAdvanceEntries(SCDesc));
140 IIVDEntry.RThroughput = MCSchedModel::getReciprocalThroughput(STI, SCDesc);
141 IIVDEntry.mayLoad = MCDesc.mayLoad();
142 IIVDEntry.mayStore = MCDesc.mayStore();
143 IIVDEntry.hasUnmodeledSideEffects = MCDesc.hasUnmodeledSideEffects();
144 }
145 }
146
147 // Construct a JSON object from a single InstructionInfoViewData object.
148 json::Object
toJSON(const InstructionInfoViewData & IIVD) const149 InstructionInfoView::toJSON(const InstructionInfoViewData &IIVD) const {
150 json::Object JO({{"NumMicroOpcodes", IIVD.NumMicroOpcodes},
151 {"Latency", IIVD.Latency},
152 {"mayLoad", IIVD.mayLoad},
153 {"mayStore", IIVD.mayStore},
154 {"hasUnmodeledSideEffects", IIVD.hasUnmodeledSideEffects}});
155 JO.try_emplace("RThroughput", IIVD.RThroughput.value_or(0.0));
156 return JO;
157 }
158
toJSON() const159 json::Value InstructionInfoView::toJSON() const {
160 ArrayRef<llvm::MCInst> Source = getSource();
161 if (!Source.size())
162 return json::Value(0);
163
164 IIVDVec IIVD(Source.size());
165 collectData(IIVD);
166
167 json::Array InstInfo;
168 for (const auto &I : enumerate(IIVD)) {
169 const InstructionInfoViewData &IIVDEntry = I.value();
170 json::Object JO = toJSON(IIVDEntry);
171 JO.try_emplace("Instruction", (unsigned)I.index());
172 InstInfo.push_back(std::move(JO));
173 }
174 return json::Object({{"InstructionList", json::Value(std::move(InstInfo))}});
175 }
176 } // namespace mca.
177 } // namespace llvm
178