1 //===-- ARMInstrInfo.cpp - ARM Instruction Information --------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the ARM implementation of the TargetInstrInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "ARMInstrInfo.h"
14 #include "ARM.h"
15 #include "ARMConstantPoolValue.h"
16 #include "ARMMachineFunctionInfo.h"
17 #include "ARMTargetMachine.h"
18 #include "MCTargetDesc/ARMAddressingModes.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/LiveVariables.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineJumpTableInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/IR/GlobalVariable.h"
27 #include "llvm/MC/MCAsmInfo.h"
28 #include "llvm/MC/MCInst.h"
29 using namespace llvm;
30
ARMInstrInfo(const ARMSubtarget & STI)31 ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI) : ARMBaseInstrInfo(STI) {}
32
33 /// Return the noop instruction to use for a noop.
getNop() const34 MCInst ARMInstrInfo::getNop() const {
35 MCInst NopInst;
36 if (hasNOP()) {
37 NopInst.setOpcode(ARM::HINT);
38 NopInst.addOperand(MCOperand::createImm(0));
39 NopInst.addOperand(MCOperand::createImm(ARMCC::AL));
40 NopInst.addOperand(MCOperand::createReg(0));
41 } else {
42 NopInst.setOpcode(ARM::MOVr);
43 NopInst.addOperand(MCOperand::createReg(ARM::R0));
44 NopInst.addOperand(MCOperand::createReg(ARM::R0));
45 NopInst.addOperand(MCOperand::createImm(ARMCC::AL));
46 NopInst.addOperand(MCOperand::createReg(0));
47 NopInst.addOperand(MCOperand::createReg(0));
48 }
49 return NopInst;
50 }
51
getUnindexedOpcode(unsigned Opc) const52 unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
53 switch (Opc) {
54 default:
55 break;
56 case ARM::LDR_PRE_IMM:
57 case ARM::LDR_PRE_REG:
58 case ARM::LDR_POST_IMM:
59 case ARM::LDR_POST_REG:
60 return ARM::LDRi12;
61 case ARM::LDRH_PRE:
62 case ARM::LDRH_POST:
63 return ARM::LDRH;
64 case ARM::LDRB_PRE_IMM:
65 case ARM::LDRB_PRE_REG:
66 case ARM::LDRB_POST_IMM:
67 case ARM::LDRB_POST_REG:
68 return ARM::LDRBi12;
69 case ARM::LDRSH_PRE:
70 case ARM::LDRSH_POST:
71 return ARM::LDRSH;
72 case ARM::LDRSB_PRE:
73 case ARM::LDRSB_POST:
74 return ARM::LDRSB;
75 case ARM::STR_PRE_IMM:
76 case ARM::STR_PRE_REG:
77 case ARM::STR_POST_IMM:
78 case ARM::STR_POST_REG:
79 return ARM::STRi12;
80 case ARM::STRH_PRE:
81 case ARM::STRH_POST:
82 return ARM::STRH;
83 case ARM::STRB_PRE_IMM:
84 case ARM::STRB_PRE_REG:
85 case ARM::STRB_POST_IMM:
86 case ARM::STRB_POST_REG:
87 return ARM::STRBi12;
88 }
89
90 return 0;
91 }
92
expandLoadStackGuard(MachineBasicBlock::iterator MI) const93 void ARMInstrInfo::expandLoadStackGuard(MachineBasicBlock::iterator MI) const {
94 MachineFunction &MF = *MI->getParent()->getParent();
95 const ARMSubtarget &Subtarget = MF.getSubtarget<ARMSubtarget>();
96 const TargetMachine &TM = MF.getTarget();
97 Module &M = *MF.getFunction().getParent();
98
99 if (M.getStackProtectorGuard() == "tls") {
100 expandLoadStackGuardBase(MI, ARM::MRC, ARM::LDRi12);
101 return;
102 }
103
104 const GlobalValue *GV =
105 cast<GlobalValue>((*MI->memoperands_begin())->getValue());
106
107 if (!Subtarget.useMovt() || Subtarget.isGVInGOT(GV)) {
108 if (TM.isPositionIndependent())
109 expandLoadStackGuardBase(MI, ARM::LDRLIT_ga_pcrel, ARM::LDRi12);
110 else
111 expandLoadStackGuardBase(MI, ARM::LDRLIT_ga_abs, ARM::LDRi12);
112 return;
113 }
114
115 if (!TM.isPositionIndependent()) {
116 expandLoadStackGuardBase(MI, ARM::MOVi32imm, ARM::LDRi12);
117 return;
118 }
119
120 if (!Subtarget.isGVIndirectSymbol(GV)) {
121 expandLoadStackGuardBase(MI, ARM::MOV_ga_pcrel, ARM::LDRi12);
122 return;
123 }
124
125 MachineBasicBlock &MBB = *MI->getParent();
126 DebugLoc DL = MI->getDebugLoc();
127 Register Reg = MI->getOperand(0).getReg();
128 MachineInstrBuilder MIB;
129
130 MIB = BuildMI(MBB, MI, DL, get(ARM::MOV_ga_pcrel_ldr), Reg)
131 .addGlobalAddress(GV, 0, ARMII::MO_NONLAZY);
132 auto Flags = MachineMemOperand::MOLoad |
133 MachineMemOperand::MODereferenceable |
134 MachineMemOperand::MOInvariant;
135 MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
136 MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 4, Align(4));
137 MIB.addMemOperand(MMO);
138 BuildMI(MBB, MI, DL, get(ARM::LDRi12), Reg)
139 .addReg(Reg, RegState::Kill)
140 .addImm(0)
141 .cloneMemRefs(*MI)
142 .add(predOps(ARMCC::AL));
143 }
144