1 //===-- Passes.h - Target independent code generation passes ----*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines interfaces to access the target independent code generation 10 // passes provided by the LLVM backend. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_CODEGEN_PASSES_H 15 #define LLVM_CODEGEN_PASSES_H 16 17 #include "llvm/Support/CodeGen.h" 18 #include <functional> 19 #include <string> 20 21 namespace llvm { 22 23 class FunctionPass; 24 class MachineFunction; 25 class MachineFunctionPass; 26 class MemoryBuffer; 27 class ModulePass; 28 class Pass; 29 class TargetMachine; 30 class TargetRegisterClass; 31 class raw_ostream; 32 33 } // End llvm namespace 34 35 // List of target independent CodeGen pass IDs. 36 namespace llvm { 37 FunctionPass *createAtomicExpandPass(); 38 39 /// createUnreachableBlockEliminationPass - The LLVM code generator does not 40 /// work well with unreachable basic blocks (what live ranges make sense for a 41 /// block that cannot be reached?). As such, a code generator should either 42 /// not instruction select unreachable blocks, or run this pass as its 43 /// last LLVM modifying pass to clean up blocks that are not reachable from 44 /// the entry block. 45 FunctionPass *createUnreachableBlockEliminationPass(); 46 47 /// createBasicBlockSections Pass - This pass assigns sections to machine 48 /// basic blocks and is enabled with -fbasic-block-sections. Buf is a memory 49 /// buffer that contains the list of functions and basic block ids to 50 /// selectively enable basic block sections. 51 MachineFunctionPass *createBasicBlockSectionsPass(const MemoryBuffer *Buf); 52 53 /// createMachineFunctionSplitterPass - This pass splits machine functions 54 /// using profile information. 55 MachineFunctionPass *createMachineFunctionSplitterPass(); 56 57 /// MachineFunctionPrinter pass - This pass prints out the machine function to 58 /// the given stream as a debugging tool. 59 MachineFunctionPass * 60 createMachineFunctionPrinterPass(raw_ostream &OS, 61 const std::string &Banner =""); 62 63 /// MIRPrinting pass - this pass prints out the LLVM IR into the given stream 64 /// using the MIR serialization format. 65 MachineFunctionPass *createPrintMIRPass(raw_ostream &OS); 66 67 /// This pass resets a MachineFunction when it has the FailedISel property 68 /// as if it was just created. 69 /// If EmitFallbackDiag is true, the pass will emit a 70 /// DiagnosticInfoISelFallback for every MachineFunction it resets. 71 /// If AbortOnFailedISel is true, abort compilation instead of resetting. 72 MachineFunctionPass *createResetMachineFunctionPass(bool EmitFallbackDiag, 73 bool AbortOnFailedISel); 74 75 /// createCodeGenPreparePass - Transform the code to expose more pattern 76 /// matching during instruction selection. 77 FunctionPass *createCodeGenPreparePass(); 78 79 /// AtomicExpandID -- Lowers atomic operations in terms of either cmpxchg 80 /// load-linked/store-conditional loops. 81 extern char &AtomicExpandID; 82 83 /// MachineLoopInfo - This pass is a loop analysis pass. 84 extern char &MachineLoopInfoID; 85 86 /// MachineDominators - This pass is a machine dominators analysis pass. 87 extern char &MachineDominatorsID; 88 89 /// MachineDominanaceFrontier - This pass is a machine dominators analysis. 90 extern char &MachineDominanceFrontierID; 91 92 /// MachineRegionInfo - This pass computes SESE regions for machine functions. 93 extern char &MachineRegionInfoPassID; 94 95 /// EdgeBundles analysis - Bundle machine CFG edges. 96 extern char &EdgeBundlesID; 97 98 /// LiveVariables pass - This pass computes the set of blocks in which each 99 /// variable is life and sets machine operand kill flags. 100 extern char &LiveVariablesID; 101 102 /// PHIElimination - This pass eliminates machine instruction PHI nodes 103 /// by inserting copy instructions. This destroys SSA information, but is the 104 /// desired input for some register allocators. This pass is "required" by 105 /// these register allocator like this: AU.addRequiredID(PHIEliminationID); 106 extern char &PHIEliminationID; 107 108 /// LiveIntervals - This analysis keeps track of the live ranges of virtual 109 /// and physical registers. 110 extern char &LiveIntervalsID; 111 112 /// LiveStacks pass. An analysis keeping track of the liveness of stack slots. 113 extern char &LiveStacksID; 114 115 /// TwoAddressInstruction - This pass reduces two-address instructions to 116 /// use two operands. This destroys SSA information but it is desired by 117 /// register allocators. 118 extern char &TwoAddressInstructionPassID; 119 120 /// ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs. 121 extern char &ProcessImplicitDefsID; 122 123 /// RegisterCoalescer - This pass merges live ranges to eliminate copies. 124 extern char &RegisterCoalescerID; 125 126 /// MachineScheduler - This pass schedules machine instructions. 127 extern char &MachineSchedulerID; 128 129 /// PostMachineScheduler - This pass schedules machine instructions postRA. 130 extern char &PostMachineSchedulerID; 131 132 /// SpillPlacement analysis. Suggest optimal placement of spill code between 133 /// basic blocks. 134 extern char &SpillPlacementID; 135 136 /// ShrinkWrap pass. Look for the best place to insert save and restore 137 // instruction and update the MachineFunctionInfo with that information. 138 extern char &ShrinkWrapID; 139 140 /// LiveRangeShrink pass. Move instruction close to its definition to shrink 141 /// the definition's live range. 142 extern char &LiveRangeShrinkID; 143 144 /// Greedy register allocator. 145 extern char &RAGreedyID; 146 147 /// Basic register allocator. 148 extern char &RABasicID; 149 150 /// VirtRegRewriter pass. Rewrite virtual registers to physical registers as 151 /// assigned in VirtRegMap. 152 extern char &VirtRegRewriterID; 153 FunctionPass *createVirtRegRewriter(bool ClearVirtRegs = true); 154 155 /// UnreachableMachineBlockElimination - This pass removes unreachable 156 /// machine basic blocks. 157 extern char &UnreachableMachineBlockElimID; 158 159 /// DeadMachineInstructionElim - This pass removes dead machine instructions. 160 extern char &DeadMachineInstructionElimID; 161 162 /// This pass adds dead/undef flags after analyzing subregister lanes. 163 extern char &DetectDeadLanesID; 164 165 /// This pass perform post-ra machine sink for COPY instructions. 166 extern char &PostRAMachineSinkingID; 167 168 /// This pass adds flow sensitive discriminators. 169 extern char &MIRAddFSDiscriminatorsID; 170 171 /// FastRegisterAllocation Pass - This pass register allocates as fast as 172 /// possible. It is best suited for debug code where live ranges are short. 173 /// 174 FunctionPass *createFastRegisterAllocator(); 175 176 /// BasicRegisterAllocation Pass - This pass implements a degenerate global 177 /// register allocator using the basic regalloc framework. 178 /// 179 FunctionPass *createBasicRegisterAllocator(); 180 181 /// Greedy register allocation pass - This pass implements a global register 182 /// allocator for optimized builds. 183 /// 184 FunctionPass *createGreedyRegisterAllocator(); 185 186 /// PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean 187 /// Quadratic Prograaming (PBQP) based register allocator. 188 /// 189 FunctionPass *createDefaultPBQPRegisterAllocator(); 190 191 /// PrologEpilogCodeInserter - This pass inserts prolog and epilog code, 192 /// and eliminates abstract frame references. 193 extern char &PrologEpilogCodeInserterID; 194 MachineFunctionPass *createPrologEpilogInserterPass(); 195 196 /// ExpandPostRAPseudos - This pass expands pseudo instructions after 197 /// register allocation. 198 extern char &ExpandPostRAPseudosID; 199 200 /// PostRAHazardRecognizer - This pass runs the post-ra hazard 201 /// recognizer. 202 extern char &PostRAHazardRecognizerID; 203 204 /// PostRAScheduler - This pass performs post register allocation 205 /// scheduling. 206 extern char &PostRASchedulerID; 207 208 /// BranchFolding - This pass performs machine code CFG based 209 /// optimizations to delete branches to branches, eliminate branches to 210 /// successor blocks (creating fall throughs), and eliminating branches over 211 /// branches. 212 extern char &BranchFolderPassID; 213 214 /// BranchRelaxation - This pass replaces branches that need to jump further 215 /// than is supported by a branch instruction. 216 extern char &BranchRelaxationPassID; 217 218 /// MachineFunctionPrinterPass - This pass prints out MachineInstr's. 219 extern char &MachineFunctionPrinterPassID; 220 221 /// MIRPrintingPass - this pass prints out the LLVM IR using the MIR 222 /// serialization format. 223 extern char &MIRPrintingPassID; 224 225 /// TailDuplicate - Duplicate blocks with unconditional branches 226 /// into tails of their predecessors. 227 extern char &TailDuplicateID; 228 229 /// Duplicate blocks with unconditional branches into tails of their 230 /// predecessors. Variant that works before register allocation. 231 extern char &EarlyTailDuplicateID; 232 233 /// MachineTraceMetrics - This pass computes critical path and CPU resource 234 /// usage in an ensemble of traces. 235 extern char &MachineTraceMetricsID; 236 237 /// EarlyIfConverter - This pass performs if-conversion on SSA form by 238 /// inserting cmov instructions. 239 extern char &EarlyIfConverterID; 240 241 /// EarlyIfPredicator - This pass performs if-conversion on SSA form by 242 /// predicating if/else block and insert select at the join point. 243 extern char &EarlyIfPredicatorID; 244 245 /// This pass performs instruction combining using trace metrics to estimate 246 /// critical-path and resource depth. 247 extern char &MachineCombinerID; 248 249 /// StackSlotColoring - This pass performs stack coloring and merging. 250 /// It merges disjoint allocas to reduce the stack size. 251 extern char &StackColoringID; 252 253 /// IfConverter - This pass performs machine code if conversion. 254 extern char &IfConverterID; 255 256 FunctionPass *createIfConverter( 257 std::function<bool(const MachineFunction &)> Ftor); 258 259 /// MachineBlockPlacement - This pass places basic blocks based on branch 260 /// probabilities. 261 extern char &MachineBlockPlacementID; 262 263 /// MachineBlockPlacementStats - This pass collects statistics about the 264 /// basic block placement using branch probabilities and block frequency 265 /// information. 266 extern char &MachineBlockPlacementStatsID; 267 268 /// GCLowering Pass - Used by gc.root to perform its default lowering 269 /// operations. 270 FunctionPass *createGCLoweringPass(); 271 272 /// ShadowStackGCLowering - Implements the custom lowering mechanism 273 /// used by the shadow stack GC. Only runs on functions which opt in to 274 /// the shadow stack collector. 275 FunctionPass *createShadowStackGCLoweringPass(); 276 277 /// GCMachineCodeAnalysis - Target-independent pass to mark safe points 278 /// in machine code. Must be added very late during code generation, just 279 /// prior to output, and importantly after all CFG transformations (such as 280 /// branch folding). 281 extern char &GCMachineCodeAnalysisID; 282 283 /// Creates a pass to print GC metadata. 284 /// 285 FunctionPass *createGCInfoPrinter(raw_ostream &OS); 286 287 /// MachineCSE - This pass performs global CSE on machine instructions. 288 extern char &MachineCSEID; 289 290 /// MIRCanonicalizer - This pass canonicalizes MIR by renaming vregs 291 /// according to the semantics of the instruction as well as hoists 292 /// code. 293 extern char &MIRCanonicalizerID; 294 295 /// ImplicitNullChecks - This pass folds null pointer checks into nearby 296 /// memory operations. 297 extern char &ImplicitNullChecksID; 298 299 /// This pass performs loop invariant code motion on machine instructions. 300 extern char &MachineLICMID; 301 302 /// This pass performs loop invariant code motion on machine instructions. 303 /// This variant works before register allocation. \see MachineLICMID. 304 extern char &EarlyMachineLICMID; 305 306 /// MachineSinking - This pass performs sinking on machine instructions. 307 extern char &MachineSinkingID; 308 309 /// MachineCopyPropagation - This pass performs copy propagation on 310 /// machine instructions. 311 extern char &MachineCopyPropagationID; 312 313 /// PeepholeOptimizer - This pass performs peephole optimizations - 314 /// like extension and comparison eliminations. 315 extern char &PeepholeOptimizerID; 316 317 /// OptimizePHIs - This pass optimizes machine instruction PHIs 318 /// to take advantage of opportunities created during DAG legalization. 319 extern char &OptimizePHIsID; 320 321 /// StackSlotColoring - This pass performs stack slot coloring. 322 extern char &StackSlotColoringID; 323 324 /// This pass lays out funclets contiguously. 325 extern char &FuncletLayoutID; 326 327 /// This pass inserts the XRay instrumentation sleds if they are supported by 328 /// the target platform. 329 extern char &XRayInstrumentationID; 330 331 /// This pass inserts FEntry calls 332 extern char &FEntryInserterID; 333 334 /// This pass implements the "patchable-function" attribute. 335 extern char &PatchableFunctionID; 336 337 /// createStackProtectorPass - This pass adds stack protectors to functions. 338 /// 339 FunctionPass *createStackProtectorPass(); 340 341 /// createMachineVerifierPass - This pass verifies cenerated machine code 342 /// instructions for correctness. 343 /// 344 FunctionPass *createMachineVerifierPass(const std::string& Banner); 345 346 /// createDwarfEHPass - This pass mulches exception handling code into a form 347 /// adapted to code generation. Required if using dwarf exception handling. 348 FunctionPass *createDwarfEHPass(CodeGenOpt::Level OptLevel); 349 350 /// createWinEHPass - Prepares personality functions used by MSVC on Windows, 351 /// in addition to the Itanium LSDA based personalities. 352 FunctionPass *createWinEHPass(bool DemoteCatchSwitchPHIOnly = false); 353 354 /// createSjLjEHPreparePass - This pass adapts exception handling code to use 355 /// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow. 356 /// 357 FunctionPass *createSjLjEHPreparePass(const TargetMachine *TM); 358 359 /// createWasmEHPass - This pass adapts exception handling code to use 360 /// WebAssembly's exception handling scheme. 361 FunctionPass *createWasmEHPass(); 362 363 /// LocalStackSlotAllocation - This pass assigns local frame indices to stack 364 /// slots relative to one another and allocates base registers to access them 365 /// when it is estimated by the target to be out of range of normal frame 366 /// pointer or stack pointer index addressing. 367 extern char &LocalStackSlotAllocationID; 368 369 /// This pass expands pseudo-instructions, reserves registers and adjusts 370 /// machine frame information. 371 extern char &FinalizeISelID; 372 373 /// UnpackMachineBundles - This pass unpack machine instruction bundles. 374 extern char &UnpackMachineBundlesID; 375 376 FunctionPass * 377 createUnpackMachineBundles(std::function<bool(const MachineFunction &)> Ftor); 378 379 /// FinalizeMachineBundles - This pass finalize machine instruction 380 /// bundles (created earlier, e.g. during pre-RA scheduling). 381 extern char &FinalizeMachineBundlesID; 382 383 /// StackMapLiveness - This pass analyses the register live-out set of 384 /// stackmap/patchpoint intrinsics and attaches the calculated information to 385 /// the intrinsic for later emission to the StackMap. 386 extern char &StackMapLivenessID; 387 388 /// LiveDebugValues pass 389 extern char &LiveDebugValuesID; 390 391 /// createJumpInstrTables - This pass creates jump-instruction tables. 392 ModulePass *createJumpInstrTablesPass(); 393 394 /// InterleavedAccess Pass - This pass identifies and matches interleaved 395 /// memory accesses to target specific intrinsics. 396 /// 397 FunctionPass *createInterleavedAccessPass(); 398 399 /// InterleavedLoadCombines Pass - This pass identifies interleaved loads and 400 /// combines them into wide loads detectable by InterleavedAccessPass 401 /// 402 FunctionPass *createInterleavedLoadCombinePass(); 403 404 /// LowerEmuTLS - This pass generates __emutls_[vt].xyz variables for all 405 /// TLS variables for the emulated TLS model. 406 /// 407 ModulePass *createLowerEmuTLSPass(); 408 409 /// This pass lowers the \@llvm.load.relative and \@llvm.objc.* intrinsics to 410 /// instructions. This is unsafe to do earlier because a pass may combine the 411 /// constant initializer into the load, which may result in an overflowing 412 /// evaluation. 413 ModulePass *createPreISelIntrinsicLoweringPass(); 414 415 /// GlobalMerge - This pass merges internal (by default) globals into structs 416 /// to enable reuse of a base pointer by indexed addressing modes. 417 /// It can also be configured to focus on size optimizations only. 418 /// 419 Pass *createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, 420 bool OnlyOptimizeForSize = false, 421 bool MergeExternalByDefault = false); 422 423 /// This pass splits the stack into a safe stack and an unsafe stack to 424 /// protect against stack-based overflow vulnerabilities. 425 FunctionPass *createSafeStackPass(); 426 427 /// This pass detects subregister lanes in a virtual register that are used 428 /// independently of other lanes and splits them into separate virtual 429 /// registers. 430 extern char &RenameIndependentSubregsID; 431 432 /// This pass is executed POST-RA to collect which physical registers are 433 /// preserved by given machine function. 434 FunctionPass *createRegUsageInfoCollector(); 435 436 /// Return a MachineFunction pass that identifies call sites 437 /// and propagates register usage information of callee to caller 438 /// if available with PysicalRegisterUsageInfo pass. 439 FunctionPass *createRegUsageInfoPropPass(); 440 441 /// This pass performs software pipelining on machine instructions. 442 extern char &MachinePipelinerID; 443 444 /// This pass frees the memory occupied by the MachineFunction. 445 FunctionPass *createFreeMachineFunctionPass(); 446 447 /// This pass performs outlining on machine instructions directly before 448 /// printing assembly. 449 ModulePass *createMachineOutlinerPass(bool RunOnAllFunctions = true); 450 451 /// This pass expands the experimental reduction intrinsics into sequences of 452 /// shuffles. 453 FunctionPass *createExpandReductionsPass(); 454 455 // This pass replaces intrinsics operating on vector operands with calls to 456 // the corresponding function in a vector library (e.g., SVML, libmvec). 457 FunctionPass *createReplaceWithVeclibLegacyPass(); 458 459 /// This pass expands the vector predication intrinsics into unpredicated 460 /// instructions with selects or just the explicit vector length into the 461 /// predicate mask. 462 FunctionPass *createExpandVectorPredicationPass(); 463 464 // This pass expands memcmp() to load/stores. 465 FunctionPass *createExpandMemCmpPass(); 466 467 /// Creates Break False Dependencies pass. \see BreakFalseDeps.cpp 468 FunctionPass *createBreakFalseDeps(); 469 470 // This pass expands indirectbr instructions. 471 FunctionPass *createIndirectBrExpandPass(); 472 473 /// Creates CFI Instruction Inserter pass. \see CFIInstrInserter.cpp 474 FunctionPass *createCFIInstrInserter(); 475 476 /// Creates CFGuard longjmp target identification pass. 477 /// \see CFGuardLongjmp.cpp 478 FunctionPass *createCFGuardLongjmpPass(); 479 480 /// Creates EHContGuard catchret target identification pass. 481 /// \see EHContGuardCatchret.cpp 482 FunctionPass *createEHContGuardCatchretPass(); 483 484 /// Create Hardware Loop pass. \see HardwareLoops.cpp 485 FunctionPass *createHardwareLoopsPass(); 486 487 /// This pass inserts pseudo probe annotation for callsite profiling. 488 FunctionPass *createPseudoProbeInserter(); 489 490 /// Create IR Type Promotion pass. \see TypePromotion.cpp 491 FunctionPass *createTypePromotionPass(); 492 493 /// Add Flow Sensitive Discriminators. 494 FunctionPass *createMIRAddFSDiscriminatorsPass(unsigned LowBit, 495 unsigned HighBit); 496 497 /// Creates MIR Debugify pass. \see MachineDebugify.cpp 498 ModulePass *createDebugifyMachineModulePass(); 499 500 /// Creates MIR Strip Debug pass. \see MachineStripDebug.cpp 501 /// If OnlyDebugified is true then it will only strip debug info if it was 502 /// added by a Debugify pass. The module will be left unchanged if the debug 503 /// info was generated by another source such as clang. 504 ModulePass *createStripDebugMachineModulePass(bool OnlyDebugified); 505 506 /// Creates MIR Check Debug pass. \see MachineCheckDebugify.cpp 507 ModulePass *createCheckDebugMachineModulePass(); 508 509 /// The pass fixups statepoint machine instruction to replace usage of 510 /// caller saved registers with stack slots. 511 extern char &FixupStatepointCallerSavedID; 512 513 /// The pass transforms load/store <256 x i32> to AMX load/store intrinsics 514 /// or split the data to two <128 x i32>. 515 FunctionPass *createX86LowerAMXTypePass(); 516 517 /// The pass insert tile config intrinsics for AMX fast register allocation. 518 FunctionPass *createX86PreAMXConfigPass(); 519 520 /// The pass transforms amx intrinsics to scalar operation if the function has 521 /// optnone attribute or it is O0. 522 FunctionPass *createX86LowerAMXIntrinsicsPass(); 523 } // End llvm namespace 524 525 #endif 526