xref: /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/link_hwss.h (revision e4a580baf2598beeaae98d953ac7635b8700b80c)
1 /*	$NetBSD: link_hwss.h,v 1.3 2021/12/19 10:59:02 riastradh Exp $	*/
2 
3 /*
4  * Copyright 2015 Advanced Micro Devices, Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: AMD
25  *
26  */
27 
28 #ifndef __DC_LINK_HWSS_H__
29 #define __DC_LINK_HWSS_H__
30 
31 #include "inc/core_status.h"
32 
33 enum dc_status core_link_read_dpcd(
34 	struct dc_link *link,
35 	uint32_t address,
36 	uint8_t *data,
37 	uint32_t size);
38 
39 enum dc_status core_link_write_dpcd(
40 	struct dc_link *link,
41 	uint32_t address,
42 	const uint8_t *data,
43 	uint32_t size);
44 
45 struct gpio *get_hpd_gpio(struct dc_bios *dcb,
46 		struct graphics_object_id link_id,
47 		struct gpio_service *gpio_service);
48 
49 void dp_enable_link_phy(
50 	struct dc_link *link,
51 	enum signal_type signal,
52 	enum clock_source_id clock_source,
53 	const struct dc_link_settings *link_settings);
54 
55 void dp_receiver_power_ctrl(struct dc_link *link, bool on);
56 bool edp_receiver_ready_T9(struct dc_link *link);
57 bool edp_receiver_ready_T7(struct dc_link *link);
58 
59 void dp_disable_link_phy(struct dc_link *link, enum signal_type signal);
60 
61 void dp_disable_link_phy_mst(struct dc_link *link, enum signal_type signal);
62 
63 bool dp_set_hw_training_pattern(
64 	struct dc_link *link,
65 	enum dc_dp_training_pattern pattern,
66 	uint32_t offset);
67 
68 void dp_set_hw_lane_settings(
69 	struct dc_link *link,
70 	const struct link_training_settings *link_settings,
71 	uint32_t offset);
72 
73 void dp_set_hw_test_pattern(
74 	struct dc_link *link,
75 	enum dp_test_pattern test_pattern,
76 	const uint8_t *custom_pattern,
77 	uint32_t custom_pattern_size);
78 
79 void dp_retrain_link_dp_test(struct dc_link *link,
80 		struct dc_link_settings *link_setting,
81 		bool skip_video_pattern);
82 
83 #endif /* __DC_LINK_HWSS_H__ */
84