1 /* $NetBSD: kfd_mqd_manager_vi.c,v 1.3 2021/12/18 23:44:59 riastradh Exp $ */
2
3 /*
4 * Copyright 2014 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: kfd_mqd_manager_vi.c,v 1.3 2021/12/18 23:44:59 riastradh Exp $");
28
29 #include <linux/printk.h>
30 #include <linux/slab.h>
31 #include <linux/mm_types.h>
32
33 #include "kfd_priv.h"
34 #include "kfd_mqd_manager.h"
35 #include "vi_structs.h"
36 #include "gca/gfx_8_0_sh_mask.h"
37 #include "gca/gfx_8_0_enum.h"
38 #include "oss/oss_3_0_sh_mask.h"
39
40 #define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8
41
get_mqd(void * mqd)42 static inline struct vi_mqd *get_mqd(void *mqd)
43 {
44 return (struct vi_mqd *)mqd;
45 }
46
get_sdma_mqd(void * mqd)47 static inline struct vi_sdma_mqd *get_sdma_mqd(void *mqd)
48 {
49 return (struct vi_sdma_mqd *)mqd;
50 }
51
update_cu_mask(struct mqd_manager * mm,void * mqd,struct queue_properties * q)52 static void update_cu_mask(struct mqd_manager *mm, void *mqd,
53 struct queue_properties *q)
54 {
55 struct vi_mqd *m;
56 uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */
57
58 if (q->cu_mask_count == 0)
59 return;
60
61 mqd_symmetrically_map_cu_mask(mm,
62 q->cu_mask, q->cu_mask_count, se_mask);
63
64 m = get_mqd(mqd);
65 m->compute_static_thread_mgmt_se0 = se_mask[0];
66 m->compute_static_thread_mgmt_se1 = se_mask[1];
67 m->compute_static_thread_mgmt_se2 = se_mask[2];
68 m->compute_static_thread_mgmt_se3 = se_mask[3];
69
70 pr_debug("Update cu mask to %#x %#x %#x %#x\n",
71 m->compute_static_thread_mgmt_se0,
72 m->compute_static_thread_mgmt_se1,
73 m->compute_static_thread_mgmt_se2,
74 m->compute_static_thread_mgmt_se3);
75 }
76
set_priority(struct vi_mqd * m,struct queue_properties * q)77 static void set_priority(struct vi_mqd *m, struct queue_properties *q)
78 {
79 m->cp_hqd_pipe_priority = pipe_priority_map[q->priority];
80 m->cp_hqd_queue_priority = q->priority;
81 }
82
allocate_mqd(struct kfd_dev * kfd,struct queue_properties * q)83 static struct kfd_mem_obj *allocate_mqd(struct kfd_dev *kfd,
84 struct queue_properties *q)
85 {
86 struct kfd_mem_obj *mqd_mem_obj;
87
88 if (kfd_gtt_sa_allocate(kfd, sizeof(struct vi_mqd),
89 &mqd_mem_obj))
90 return NULL;
91
92 return mqd_mem_obj;
93 }
94
init_mqd(struct mqd_manager * mm,void ** mqd,struct kfd_mem_obj * mqd_mem_obj,uint64_t * gart_addr,struct queue_properties * q)95 static void init_mqd(struct mqd_manager *mm, void **mqd,
96 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
97 struct queue_properties *q)
98 {
99 uint64_t addr;
100 struct vi_mqd *m;
101
102 m = (struct vi_mqd *) mqd_mem_obj->cpu_ptr;
103 addr = mqd_mem_obj->gpu_addr;
104
105 memset(m, 0, sizeof(struct vi_mqd));
106
107 m->header = 0xC0310800;
108 m->compute_pipelinestat_enable = 1;
109 m->compute_static_thread_mgmt_se0 = 0xFFFFFFFF;
110 m->compute_static_thread_mgmt_se1 = 0xFFFFFFFF;
111 m->compute_static_thread_mgmt_se2 = 0xFFFFFFFF;
112 m->compute_static_thread_mgmt_se3 = 0xFFFFFFFF;
113
114 m->cp_hqd_persistent_state = CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK |
115 0x53 << CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT;
116
117 m->cp_mqd_control = 1 << CP_MQD_CONTROL__PRIV_STATE__SHIFT |
118 MTYPE_UC << CP_MQD_CONTROL__MTYPE__SHIFT;
119
120 m->cp_mqd_base_addr_lo = lower_32_bits(addr);
121 m->cp_mqd_base_addr_hi = upper_32_bits(addr);
122
123 m->cp_hqd_quantum = 1 << CP_HQD_QUANTUM__QUANTUM_EN__SHIFT |
124 1 << CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT |
125 10 << CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT;
126
127 set_priority(m, q);
128 m->cp_hqd_eop_rptr = 1 << CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT;
129
130 if (q->format == KFD_QUEUE_FORMAT_AQL)
131 m->cp_hqd_iq_rptr = 1;
132
133 if (q->tba_addr) {
134 m->compute_tba_lo = lower_32_bits(q->tba_addr >> 8);
135 m->compute_tba_hi = upper_32_bits(q->tba_addr >> 8);
136 m->compute_tma_lo = lower_32_bits(q->tma_addr >> 8);
137 m->compute_tma_hi = upper_32_bits(q->tma_addr >> 8);
138 m->compute_pgm_rsrc2 |=
139 (1 << COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT);
140 }
141
142 if (mm->dev->cwsr_enabled && q->ctx_save_restore_area_address) {
143 m->cp_hqd_persistent_state |=
144 (1 << CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT);
145 m->cp_hqd_ctx_save_base_addr_lo =
146 lower_32_bits(q->ctx_save_restore_area_address);
147 m->cp_hqd_ctx_save_base_addr_hi =
148 upper_32_bits(q->ctx_save_restore_area_address);
149 m->cp_hqd_ctx_save_size = q->ctx_save_restore_area_size;
150 m->cp_hqd_cntl_stack_size = q->ctl_stack_size;
151 m->cp_hqd_cntl_stack_offset = q->ctl_stack_size;
152 m->cp_hqd_wg_state_offset = q->ctl_stack_size;
153 }
154
155 *mqd = m;
156 if (gart_addr)
157 *gart_addr = addr;
158 mm->update_mqd(mm, m, q);
159 }
160
load_mqd(struct mqd_manager * mm,void * mqd,uint32_t pipe_id,uint32_t queue_id,struct queue_properties * p,struct mm_struct * mms)161 static int load_mqd(struct mqd_manager *mm, void *mqd,
162 uint32_t pipe_id, uint32_t queue_id,
163 struct queue_properties *p, struct mm_struct *mms)
164 {
165 /* AQL write pointer counts in 64B packets, PM4/CP counts in dwords. */
166 uint32_t wptr_shift = (p->format == KFD_QUEUE_FORMAT_AQL ? 4 : 0);
167 uint32_t wptr_mask = (uint32_t)((p->queue_size / 4) - 1);
168
169 return mm->dev->kfd2kgd->hqd_load(mm->dev->kgd, mqd, pipe_id, queue_id,
170 (uint32_t __user *)p->write_ptr,
171 wptr_shift, wptr_mask, mms);
172 }
173
__update_mqd(struct mqd_manager * mm,void * mqd,struct queue_properties * q,unsigned int mtype,unsigned int atc_bit)174 static void __update_mqd(struct mqd_manager *mm, void *mqd,
175 struct queue_properties *q, unsigned int mtype,
176 unsigned int atc_bit)
177 {
178 struct vi_mqd *m;
179
180 m = get_mqd(mqd);
181
182 m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT |
183 atc_bit << CP_HQD_PQ_CONTROL__PQ_ATC__SHIFT |
184 mtype << CP_HQD_PQ_CONTROL__MTYPE__SHIFT;
185 m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1;
186 pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);
187
188 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
189 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);
190
191 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
192 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
193 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr);
194 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr);
195
196 m->cp_hqd_pq_doorbell_control =
197 q->doorbell_off <<
198 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT;
199 pr_debug("cp_hqd_pq_doorbell_control 0x%x\n",
200 m->cp_hqd_pq_doorbell_control);
201
202 m->cp_hqd_eop_control = atc_bit << CP_HQD_EOP_CONTROL__EOP_ATC__SHIFT |
203 mtype << CP_HQD_EOP_CONTROL__MTYPE__SHIFT;
204
205 m->cp_hqd_ib_control = atc_bit << CP_HQD_IB_CONTROL__IB_ATC__SHIFT |
206 3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT |
207 mtype << CP_HQD_IB_CONTROL__MTYPE__SHIFT;
208
209 /*
210 * HW does not clamp this field correctly. Maximum EOP queue size
211 * is constrained by per-SE EOP done signal count, which is 8-bit.
212 * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit
213 * more than (EOP entry count - 1) so a queue size of 0x800 dwords
214 * is safe, giving a maximum field value of 0xA.
215 */
216 m->cp_hqd_eop_control |= min(0xA,
217 order_base_2(q->eop_ring_buffer_size / 4) - 1);
218 m->cp_hqd_eop_base_addr_lo =
219 lower_32_bits(q->eop_ring_buffer_address >> 8);
220 m->cp_hqd_eop_base_addr_hi =
221 upper_32_bits(q->eop_ring_buffer_address >> 8);
222
223 m->cp_hqd_iq_timer = atc_bit << CP_HQD_IQ_TIMER__IQ_ATC__SHIFT |
224 mtype << CP_HQD_IQ_TIMER__MTYPE__SHIFT;
225
226 m->cp_hqd_vmid = q->vmid;
227
228 if (q->format == KFD_QUEUE_FORMAT_AQL) {
229 m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK |
230 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT;
231 }
232
233 if (mm->dev->cwsr_enabled && q->ctx_save_restore_area_address)
234 m->cp_hqd_ctx_save_control =
235 atc_bit << CP_HQD_CTX_SAVE_CONTROL__ATC__SHIFT |
236 mtype << CP_HQD_CTX_SAVE_CONTROL__MTYPE__SHIFT;
237
238 update_cu_mask(mm, mqd, q);
239 set_priority(m, q);
240
241 q->is_active = QUEUE_IS_ACTIVE(*q);
242 }
243
244
update_mqd(struct mqd_manager * mm,void * mqd,struct queue_properties * q)245 static void update_mqd(struct mqd_manager *mm, void *mqd,
246 struct queue_properties *q)
247 {
248 __update_mqd(mm, mqd, q, MTYPE_CC, 1);
249 }
250
update_mqd_tonga(struct mqd_manager * mm,void * mqd,struct queue_properties * q)251 static void update_mqd_tonga(struct mqd_manager *mm, void *mqd,
252 struct queue_properties *q)
253 {
254 __update_mqd(mm, mqd, q, MTYPE_UC, 0);
255 }
256
destroy_mqd(struct mqd_manager * mm,void * mqd,enum kfd_preempt_type type,unsigned int timeout,uint32_t pipe_id,uint32_t queue_id)257 static int destroy_mqd(struct mqd_manager *mm, void *mqd,
258 enum kfd_preempt_type type,
259 unsigned int timeout, uint32_t pipe_id,
260 uint32_t queue_id)
261 {
262 return mm->dev->kfd2kgd->hqd_destroy
263 (mm->dev->kgd, mqd, type, timeout,
264 pipe_id, queue_id);
265 }
266
free_mqd(struct mqd_manager * mm,void * mqd,struct kfd_mem_obj * mqd_mem_obj)267 static void free_mqd(struct mqd_manager *mm, void *mqd,
268 struct kfd_mem_obj *mqd_mem_obj)
269 {
270 kfd_gtt_sa_free(mm->dev, mqd_mem_obj);
271 }
272
is_occupied(struct mqd_manager * mm,void * mqd,uint64_t queue_address,uint32_t pipe_id,uint32_t queue_id)273 static bool is_occupied(struct mqd_manager *mm, void *mqd,
274 uint64_t queue_address, uint32_t pipe_id,
275 uint32_t queue_id)
276 {
277 return mm->dev->kfd2kgd->hqd_is_occupied(
278 mm->dev->kgd, queue_address,
279 pipe_id, queue_id);
280 }
281
get_wave_state(struct mqd_manager * mm,void * mqd,void __user * ctl_stack,u32 * ctl_stack_used_size,u32 * save_area_used_size)282 static int get_wave_state(struct mqd_manager *mm, void *mqd,
283 void __user *ctl_stack,
284 u32 *ctl_stack_used_size,
285 u32 *save_area_used_size)
286 {
287 struct vi_mqd *m;
288
289 m = get_mqd(mqd);
290
291 *ctl_stack_used_size = m->cp_hqd_cntl_stack_size -
292 m->cp_hqd_cntl_stack_offset;
293 *save_area_used_size = m->cp_hqd_wg_state_offset -
294 m->cp_hqd_cntl_stack_size;
295
296 /* Control stack is not copied to user mode for GFXv8 because
297 * it's part of the context save area that is already
298 * accessible to user mode
299 */
300
301 return 0;
302 }
303
init_mqd_hiq(struct mqd_manager * mm,void ** mqd,struct kfd_mem_obj * mqd_mem_obj,uint64_t * gart_addr,struct queue_properties * q)304 static void init_mqd_hiq(struct mqd_manager *mm, void **mqd,
305 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
306 struct queue_properties *q)
307 {
308 struct vi_mqd *m;
309 init_mqd(mm, mqd, mqd_mem_obj, gart_addr, q);
310
311 m = get_mqd(*mqd);
312
313 m->cp_hqd_pq_control |= 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT |
314 1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT;
315 }
316
update_mqd_hiq(struct mqd_manager * mm,void * mqd,struct queue_properties * q)317 static void update_mqd_hiq(struct mqd_manager *mm, void *mqd,
318 struct queue_properties *q)
319 {
320 __update_mqd(mm, mqd, q, MTYPE_UC, 0);
321 }
322
init_mqd_sdma(struct mqd_manager * mm,void ** mqd,struct kfd_mem_obj * mqd_mem_obj,uint64_t * gart_addr,struct queue_properties * q)323 static void init_mqd_sdma(struct mqd_manager *mm, void **mqd,
324 struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
325 struct queue_properties *q)
326 {
327 struct vi_sdma_mqd *m;
328
329 m = (struct vi_sdma_mqd *) mqd_mem_obj->cpu_ptr;
330
331 memset(m, 0, sizeof(struct vi_sdma_mqd));
332
333 *mqd = m;
334 if (gart_addr)
335 *gart_addr = mqd_mem_obj->gpu_addr;
336
337 mm->update_mqd(mm, m, q);
338 }
339
load_mqd_sdma(struct mqd_manager * mm,void * mqd,uint32_t pipe_id,uint32_t queue_id,struct queue_properties * p,struct mm_struct * mms)340 static int load_mqd_sdma(struct mqd_manager *mm, void *mqd,
341 uint32_t pipe_id, uint32_t queue_id,
342 struct queue_properties *p, struct mm_struct *mms)
343 {
344 return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->kgd, mqd,
345 (uint32_t __user *)p->write_ptr,
346 mms);
347 }
348
update_mqd_sdma(struct mqd_manager * mm,void * mqd,struct queue_properties * q)349 static void update_mqd_sdma(struct mqd_manager *mm, void *mqd,
350 struct queue_properties *q)
351 {
352 struct vi_sdma_mqd *m;
353
354 m = get_sdma_mqd(mqd);
355 m->sdmax_rlcx_rb_cntl = order_base_2(q->queue_size / 4)
356 << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
357 q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT |
358 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
359 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT;
360
361 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8);
362 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8);
363 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
364 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
365 m->sdmax_rlcx_doorbell =
366 q->doorbell_off << SDMA0_RLC0_DOORBELL__OFFSET__SHIFT;
367
368 m->sdmax_rlcx_virtual_addr = q->sdma_vm_addr;
369
370 m->sdma_engine_id = q->sdma_engine_id;
371 m->sdma_queue_id = q->sdma_queue_id;
372
373 q->is_active = QUEUE_IS_ACTIVE(*q);
374 }
375
376 /*
377 * * preempt type here is ignored because there is only one way
378 * * to preempt sdma queue
379 */
destroy_mqd_sdma(struct mqd_manager * mm,void * mqd,enum kfd_preempt_type type,unsigned int timeout,uint32_t pipe_id,uint32_t queue_id)380 static int destroy_mqd_sdma(struct mqd_manager *mm, void *mqd,
381 enum kfd_preempt_type type,
382 unsigned int timeout, uint32_t pipe_id,
383 uint32_t queue_id)
384 {
385 return mm->dev->kfd2kgd->hqd_sdma_destroy(mm->dev->kgd, mqd, timeout);
386 }
387
is_occupied_sdma(struct mqd_manager * mm,void * mqd,uint64_t queue_address,uint32_t pipe_id,uint32_t queue_id)388 static bool is_occupied_sdma(struct mqd_manager *mm, void *mqd,
389 uint64_t queue_address, uint32_t pipe_id,
390 uint32_t queue_id)
391 {
392 return mm->dev->kfd2kgd->hqd_sdma_is_occupied(mm->dev->kgd, mqd);
393 }
394
395 #if defined(CONFIG_DEBUG_FS)
396
debugfs_show_mqd(struct seq_file * m,void * data)397 static int debugfs_show_mqd(struct seq_file *m, void *data)
398 {
399 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4,
400 data, sizeof(struct vi_mqd), false);
401 return 0;
402 }
403
debugfs_show_mqd_sdma(struct seq_file * m,void * data)404 static int debugfs_show_mqd_sdma(struct seq_file *m, void *data)
405 {
406 seq_hex_dump(m, " ", DUMP_PREFIX_OFFSET, 32, 4,
407 data, sizeof(struct vi_sdma_mqd), false);
408 return 0;
409 }
410
411 #endif
412
mqd_manager_init_vi(enum KFD_MQD_TYPE type,struct kfd_dev * dev)413 struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type,
414 struct kfd_dev *dev)
415 {
416 struct mqd_manager *mqd;
417
418 if (WARN_ON(type >= KFD_MQD_TYPE_MAX))
419 return NULL;
420
421 mqd = kzalloc(sizeof(*mqd), GFP_KERNEL);
422 if (!mqd)
423 return NULL;
424
425 mqd->dev = dev;
426
427 switch (type) {
428 case KFD_MQD_TYPE_CP:
429 mqd->allocate_mqd = allocate_mqd;
430 mqd->init_mqd = init_mqd;
431 mqd->free_mqd = free_mqd;
432 mqd->load_mqd = load_mqd;
433 mqd->update_mqd = update_mqd;
434 mqd->destroy_mqd = destroy_mqd;
435 mqd->is_occupied = is_occupied;
436 mqd->get_wave_state = get_wave_state;
437 mqd->mqd_size = sizeof(struct vi_mqd);
438 #if defined(CONFIG_DEBUG_FS)
439 mqd->debugfs_show_mqd = debugfs_show_mqd;
440 #endif
441 break;
442 case KFD_MQD_TYPE_HIQ:
443 mqd->allocate_mqd = allocate_hiq_mqd;
444 mqd->init_mqd = init_mqd_hiq;
445 mqd->free_mqd = free_mqd_hiq_sdma;
446 mqd->load_mqd = load_mqd;
447 mqd->update_mqd = update_mqd_hiq;
448 mqd->destroy_mqd = destroy_mqd;
449 mqd->is_occupied = is_occupied;
450 mqd->mqd_size = sizeof(struct vi_mqd);
451 #if defined(CONFIG_DEBUG_FS)
452 mqd->debugfs_show_mqd = debugfs_show_mqd;
453 #endif
454 break;
455 case KFD_MQD_TYPE_DIQ:
456 mqd->allocate_mqd = allocate_mqd;
457 mqd->init_mqd = init_mqd_hiq;
458 mqd->free_mqd = free_mqd;
459 mqd->load_mqd = load_mqd;
460 mqd->update_mqd = update_mqd_hiq;
461 mqd->destroy_mqd = destroy_mqd;
462 mqd->is_occupied = is_occupied;
463 mqd->mqd_size = sizeof(struct vi_mqd);
464 #if defined(CONFIG_DEBUG_FS)
465 mqd->debugfs_show_mqd = debugfs_show_mqd;
466 #endif
467 break;
468 case KFD_MQD_TYPE_SDMA:
469 mqd->allocate_mqd = allocate_sdma_mqd;
470 mqd->init_mqd = init_mqd_sdma;
471 mqd->free_mqd = free_mqd_hiq_sdma;
472 mqd->load_mqd = load_mqd_sdma;
473 mqd->update_mqd = update_mqd_sdma;
474 mqd->destroy_mqd = destroy_mqd_sdma;
475 mqd->is_occupied = is_occupied_sdma;
476 mqd->mqd_size = sizeof(struct vi_sdma_mqd);
477 #if defined(CONFIG_DEBUG_FS)
478 mqd->debugfs_show_mqd = debugfs_show_mqd_sdma;
479 #endif
480 break;
481 default:
482 kfree(mqd);
483 return NULL;
484 }
485
486 return mqd;
487 }
488
mqd_manager_init_vi_tonga(enum KFD_MQD_TYPE type,struct kfd_dev * dev)489 struct mqd_manager *mqd_manager_init_vi_tonga(enum KFD_MQD_TYPE type,
490 struct kfd_dev *dev)
491 {
492 struct mqd_manager *mqd;
493
494 mqd = mqd_manager_init_vi(type, dev);
495 if (!mqd)
496 return NULL;
497 if (type == KFD_MQD_TYPE_CP)
498 mqd->update_mqd = update_mqd_tonga;
499 return mqd;
500 }
501