1 /* $NetBSD: ixgbe_dcb.h,v 1.9 2021/12/24 05:02:11 msaitoh Exp $ */ 2 /****************************************************************************** 3 SPDX-License-Identifier: BSD-3-Clause 4 5 Copyright (c) 2001-2020, Intel Corporation 6 All rights reserved. 7 8 Redistribution and use in source and binary forms, with or without 9 modification, are permitted provided that the following conditions are met: 10 11 1. Redistributions of source code must retain the above copyright notice, 12 this list of conditions and the following disclaimer. 13 14 2. Redistributions in binary form must reproduce the above copyright 15 notice, this list of conditions and the following disclaimer in the 16 documentation and/or other materials provided with the distribution. 17 18 3. Neither the name of the Intel Corporation nor the names of its 19 contributors may be used to endorse or promote products derived from 20 this software without specific prior written permission. 21 22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 26 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 POSSIBILITY OF SUCH DAMAGE. 33 34 ******************************************************************************/ 35 /*$FreeBSD: head/sys/dev/ixgbe/ixgbe_dcb.h 326022 2017-11-20 19:36:21Z pfg $*/ 36 37 #ifndef _IXGBE_DCB_H_ 38 #define _IXGBE_DCB_H_ 39 40 #include "ixgbe_type.h" 41 42 /* DCB defines */ 43 /* DCB credit calculation defines */ 44 #define IXGBE_DCB_CREDIT_QUANTUM 64 45 #define IXGBE_DCB_MAX_CREDIT_REFILL 511 /* 0x1FF * 64B = 32704B */ 46 #define IXGBE_DCB_MAX_TSO_SIZE (32 * 1024) /* Max TSO pkt size in DCB*/ 47 #define IXGBE_DCB_MAX_CREDIT 4095 /* Maximum credit supported: 256KB * 1024 / 64B */ 48 49 /* 513 for 32KB TSO packet */ 50 #define IXGBE_DCB_MIN_TSO_CREDIT \ 51 ((IXGBE_DCB_MAX_TSO_SIZE / IXGBE_DCB_CREDIT_QUANTUM) + 1) 52 53 /* DCB configuration defines */ 54 #define IXGBE_DCB_MAX_USER_PRIORITY 8 55 #define IXGBE_DCB_MAX_BW_GROUP 8 56 #define IXGBE_DCB_BW_PERCENT 100 57 58 #define IXGBE_DCB_TX_CONFIG 0 59 #define IXGBE_DCB_RX_CONFIG 1 60 61 /* DCB capability defines */ 62 #define IXGBE_DCB_PG_SUPPORT 0x00000001 63 #define IXGBE_DCB_PFC_SUPPORT 0x00000002 64 #define IXGBE_DCB_BCN_SUPPORT 0x00000004 65 #define IXGBE_DCB_UP2TC_SUPPORT 0x00000008 66 #define IXGBE_DCB_GSP_SUPPORT 0x00000010 67 68 struct ixgbe_dcb_support { 69 u32 capabilities; /* DCB capabilities */ 70 71 /* Each bit represents a number of TCs configurable in the hw. 72 * If 8 traffic classes can be configured, the value is 0x80. */ 73 u8 traffic_classes; 74 u8 pfc_traffic_classes; 75 }; 76 77 enum ixgbe_dcb_tsa { 78 ixgbe_dcb_tsa_ets = 0, 79 ixgbe_dcb_tsa_group_strict_cee, 80 ixgbe_dcb_tsa_strict 81 }; 82 83 /* Traffic class bandwidth allocation per direction */ 84 struct ixgbe_dcb_tc_path { 85 u8 bwg_id; /* Bandwidth Group (BWG) ID */ 86 u8 bwg_percent; /* % of BWG's bandwidth */ 87 u8 link_percent; /* % of link bandwidth */ 88 u8 up_to_tc_bitmap; /* User Priority to Traffic Class mapping */ 89 u16 data_credits_refill; /* Credit refill amount in 64B granularity */ 90 u16 data_credits_max; /* Max credits for a configured packet buffer 91 * in 64B granularity.*/ 92 enum ixgbe_dcb_tsa tsa; /* Link or Group Strict Priority */ 93 }; 94 95 enum ixgbe_dcb_pfc { 96 ixgbe_dcb_pfc_disabled = 0, 97 ixgbe_dcb_pfc_enabled, 98 ixgbe_dcb_pfc_enabled_txonly, 99 ixgbe_dcb_pfc_enabled_rxonly 100 }; 101 102 /* Traffic class configuration */ 103 struct ixgbe_dcb_tc_config { 104 struct ixgbe_dcb_tc_path path[2]; /* One each for Tx/Rx */ 105 enum ixgbe_dcb_pfc pfc; /* Class based flow control setting */ 106 107 u16 desc_credits_max; /* For Tx Descriptor arbitration */ 108 u8 tc; /* Traffic class (TC) */ 109 }; 110 111 enum ixgbe_dcb_pba { 112 /* PBA[0-7] each use 64KB FIFO */ 113 ixgbe_dcb_pba_equal = PBA_STRATEGY_EQUAL, 114 /* PBA[0-3] each use 80KB, PBA[4-7] each use 48KB */ 115 ixgbe_dcb_pba_80_48 = PBA_STRATEGY_WEIGHTED 116 }; 117 118 struct ixgbe_dcb_num_tcs { 119 u8 pg_tcs; 120 u8 pfc_tcs; 121 }; 122 123 struct ixgbe_dcb_config { 124 struct ixgbe_dcb_tc_config tc_config[IXGBE_DCB_MAX_TRAFFIC_CLASS]; 125 struct ixgbe_dcb_support support; 126 struct ixgbe_dcb_num_tcs num_tcs; 127 u8 bw_percentage[2][IXGBE_DCB_MAX_BW_GROUP]; /* One each for Tx/Rx */ 128 bool pfc_mode_enable; 129 bool round_robin_enable; 130 131 enum ixgbe_dcb_pba rx_pba_cfg; 132 133 u32 dcb_cfg_version; /* Not used...OS-specific? */ 134 u32 link_speed; /* For bandwidth allocation validation purpose */ 135 bool vt_mode; 136 }; 137 138 /* DCB driver APIs */ 139 140 /* DCB rule checking */ 141 s32 ixgbe_dcb_check_config_cee(struct ixgbe_dcb_config *); 142 143 /* DCB credits calculation */ 144 s32 ixgbe_dcb_calculate_tc_credits(u8 *, u16 *, u16 *, int); 145 s32 ixgbe_dcb_calculate_tc_credits_cee(struct ixgbe_hw *, 146 struct ixgbe_dcb_config *, u32, u8); 147 148 /* DCB PFC */ 149 s32 ixgbe_dcb_config_pfc(struct ixgbe_hw *, u8, u8 *); 150 s32 ixgbe_dcb_config_pfc_cee(struct ixgbe_hw *, struct ixgbe_dcb_config *); 151 152 /* DCB stats */ 153 s32 ixgbe_dcb_config_tc_stats(struct ixgbe_hw *); 154 s32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw *, struct ixgbe_hw_stats *, u8); 155 s32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw *, struct ixgbe_hw_stats *, u8); 156 157 /* DCB config arbiters */ 158 s32 ixgbe_dcb_config_tx_desc_arbiter_cee(struct ixgbe_hw *, 159 struct ixgbe_dcb_config *); 160 s32 ixgbe_dcb_config_tx_data_arbiter_cee(struct ixgbe_hw *, 161 struct ixgbe_dcb_config *); 162 s32 ixgbe_dcb_config_rx_arbiter_cee(struct ixgbe_hw *, 163 struct ixgbe_dcb_config *); 164 165 /* DCB unpack routines */ 166 void ixgbe_dcb_unpack_pfc_cee(struct ixgbe_dcb_config *, u8 *, u8 *); 167 void ixgbe_dcb_unpack_refill_cee(struct ixgbe_dcb_config *, int, u16 *); 168 void ixgbe_dcb_unpack_max_cee(struct ixgbe_dcb_config *, u16 *); 169 void ixgbe_dcb_unpack_bwgid_cee(struct ixgbe_dcb_config *, int, u8 *); 170 void ixgbe_dcb_unpack_tsa_cee(struct ixgbe_dcb_config *, int, u8 *); 171 void ixgbe_dcb_unpack_map_cee(struct ixgbe_dcb_config *, int, u8 *); 172 u8 ixgbe_dcb_get_tc_from_up(struct ixgbe_dcb_config *, int, u8); 173 174 /* DCB initialization */ 175 s32 ixgbe_dcb_hw_config(struct ixgbe_hw *, u16 *, u16 *, u8 *, u8 *, u8 *); 176 s32 ixgbe_dcb_hw_config_cee(struct ixgbe_hw *, struct ixgbe_dcb_config *); 177 #endif /* _IXGBE_DCB_H_ */ 178