1 /* $NetBSD: iris_zs.h,v 1.1 2019/01/12 16:44:47 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 2018 Naruaki Etomi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* 29 * Silicon Graphics "IRIS" series MIPS processors machine bootloader. 30 */ 31 32 /* The layout of this is hardware-dependent (padding, order). */ 33 struct zschan { 34 uint8_t pad1[3]; 35 volatile uint8_t zc_csr; /* ctrl,status, and indirect access */ 36 uint8_t pad2[3]; 37 volatile uint8_t zc_data; /* data */ 38 }; 39 40 struct zsdevice { 41 struct zschan zs_chan_b; 42 struct zschan zs_chan_a; 43 }; 44 45 void *zs_init(int, int); 46 int zscngetc(void *); 47 void zscnputc(void *, int); 48 int zscnscanc(void *); 49