1 /* $NetBSD: iris_machdep.h,v 1.1 2019/01/12 16:44:47 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 2018 Naruaki Etomi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* 29 * Silicon Graphics "IRIS" series MIPS processors machine bootloader. 30 */ 31 32 #include <sys/param.h> 33 #include <lib/libsa/stand.h> 34 #include "iris_scsivar.h" 35 36 /* iris_boot.c */ 37 void again(void); 38 void reboot(void); 39 40 /* iris_parse.c */ 41 void parse(char **, char *); 42 43 /* iris_autoconf.c */ 44 void find_devs(void); 45 46 /* iris_start.S */ 47 void romrestart(void); 48 49 /* iris_cons.c */ 50 char *cninit(int *, int *); 51 int cngetc(void); 52 void cnputc(int); 53 int cnscan(void); 54 55 /* iris_scsi.c */ 56 void wd33c93_init(void *, void*); 57 int wd33c93_go(struct wd33c93_softc *, uint8_t *, size_t, uint8_t *, size_t *); 58 59 /* iris_scsictl.c */ 60 int scsi_test_unit_rdy(void); 61 int scsi_read_capacity(uint8_t *, size_t); 62 int scsi_read(uint8_t *, size_t, daddr_t, size_t); 63 int scsi_write(uint8_t *, size_t, daddr_t, size_t); 64 65 #define INDIGO_R3K_MODE 66 67 #ifdef INDIGO_R3K_MODE 68 #define ZS_ADDR 0x1fb80d10 69 #define SCSIA_ADDR 0x1FB80122 70 #define SCSID_ADDR 0x1FB80126 71 72 /* Target is Personal IRIS R3000 36MHz. */ 73 #define CPUSPEED 36 74 #endif 75 76 #ifdef INDIGO_R4K_MODE 77 #define ZS_ADDR 0x1fb80d10 78 #define SCSIA_ADDR 0x1FB80122 79 #define SCSID_ADDR 0x1FB80126 80 81 /* Target is IRIS Indigo R4000 100MHz. */ 82 #define CPUSPEED 100 83 #endif 84 85 #ifdef INDY_MODE 86 #define ZS_ADDR 0x1fbd9830 87 #define SCSIA_ADDR 0x1FBC0003 88 #define SCSID_ADDR 0x1FBC0007 89 90 /* Target is Indy 180MHz. */ 91 #define CPUSPEED 180 92 #endif 93 94 #define DELAY(n) \ 95 do { \ 96 register int __N = (CPUSPEED) / 2 * n; \ 97 do { \ 98 __asm("addiu %0,%1,-1" : "=r" (__N) : "0" (__N)); \ 99 } while (__N > 0); \ 100 } while (/* CONSTCOND */ 0) 101