1 /* $NetBSD: iq80310_pci.c,v 1.16 2019/03/01 09:25:59 msaitoh Exp $ */
2
3 /*
4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
23 * written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 /*
39 * IQ80310 PCI interrupt support, using he i80312 Companion I/O chip.
40 */
41
42 #include <sys/cdefs.h>
43 __KERNEL_RCSID(0, "$NetBSD: iq80310_pci.c,v 1.16 2019/03/01 09:25:59 msaitoh Exp $");
44
45 #include <sys/param.h>
46 #include <sys/systm.h>
47 #include <sys/device.h>
48
49 #include <machine/autoconf.h>
50 #include <sys/bus.h>
51
52 #include <evbarm/iq80310/iq80310reg.h>
53 #include <evbarm/iq80310/iq80310var.h>
54
55 #include <arm/xscale/i80312reg.h>
56 #include <arm/xscale/i80312var.h>
57
58 #include <dev/pci/pcidevs.h>
59 #include <dev/pci/ppbreg.h>
60
61 int iq80310_pci_intr_map(const struct pci_attach_args *,
62 pci_intr_handle_t *);
63 const char *iq80310_pci_intr_string(void *, pci_intr_handle_t, char *, size_t);
64 const struct evcnt *iq80310_pci_intr_evcnt(void *, pci_intr_handle_t);
65 void *iq80310_pci_intr_establish(void *, pci_intr_handle_t,
66 int, int (*func)(void *), void *, const char *);
67 void iq80310_pci_intr_disestablish(void *, void *);
68
69 void
iq80310_pci_init(pci_chipset_tag_t pc,void * cookie)70 iq80310_pci_init(pci_chipset_tag_t pc, void *cookie)
71 {
72
73 pc->pc_intr_v = cookie; /* the i80312 softc */
74 pc->pc_intr_map = iq80310_pci_intr_map;
75 pc->pc_intr_string = iq80310_pci_intr_string;
76 pc->pc_intr_evcnt = iq80310_pci_intr_evcnt;
77 pc->pc_intr_establish = iq80310_pci_intr_establish;
78 pc->pc_intr_disestablish = iq80310_pci_intr_disestablish;
79 }
80
81 #if defined(IOP310_TEAMASA_NPWR)
82 int
iq80310_pci_intr_map(const struct pci_attach_args * pa,pci_intr_handle_t * ihp)83 iq80310_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
84 {
85 struct i80312_softc *sc = pa->pa_pc->pc_intr_v;
86 pcireg_t reg;
87 int sbus;
88
89 /*
90 * The Npwr routes #INTA of the on-board PCI devices directly
91 * through the CPLD. There is no PCI-PCI bridge and no PCI
92 * slots on the Npwr.
93 *
94 * We also expect the devices to be on the Secondary side of
95 * the i80312.
96 */
97
98 reg = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PCI_BRIDGE_BUS_REG);
99 sbus = PCI_BRIDGE_BUS_NUM_SECONDARY(reg);
100
101 if (pa->pa_bus != sbus) {
102 printf("iq80310_pci_intr_map: %d/%d/%d not on Secondary bus\n",
103 pa->pa_bus, pa->pa_device, pa->pa_function);
104 return (1);
105 }
106
107 switch (pa->pa_device) {
108 case 5: /* LSI 53c1010 SCSI */
109 *ihp = XINT3_IRQ(2);
110 break;
111 case 6: /* Intel i82544GC Gig-E #1 */
112 *ihp = XINT3_IRQ(1);
113 break;
114 case 7: /* Intel i82544GC Gig-E #2 */
115 *ihp = XINT3_IRQ(4);
116 break;
117 default:
118 printf("iq80310_pci_intr_map: no mapping for %d/%d/%d\n",
119 pa->pa_bus, pa->pa_device, pa->pa_function);
120 return (1);
121 }
122
123 return (0);
124 }
125 #else /* Default to stock IQ80310 */
126 int
iq80310_pci_intr_map(const struct pci_attach_args * pa,pci_intr_handle_t * ihp)127 iq80310_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
128 {
129 struct i80312_softc *sc = pa->pa_pc->pc_intr_v;
130 pcitag_t tag;
131 pcireg_t reg;
132 int sbus, pbus;
133
134 /*
135 * Mapping of PCI interrupts on the IQ80310 is pretty easy; there
136 * is a single interrupt line for all PCI devices on pre-F boards,
137 * and an interrupt line for each INTx# signal on F and later boards.
138 *
139 * The only exception is the on-board Ethernet; this devices has
140 * its own dedicated interrupt line. The location of this device
141 * looks like this:
142 *
143 * 80312 Secondary -> PPB at dev #7 -> i82559 at dev #0
144 *
145 * In order to determine if we're mapping the interrupt for the
146 * on-board Ethernet, we must read the Secondary Bus # of the
147 * i80312, then use that to read the Secondary Bus # of the
148 * 21154 PPB. At that point, we know that b/d/f of the i82559,
149 * and can determine if we're looking at that device.
150 */
151
152 reg = bus_space_read_4(sc->sc_st, sc->sc_ppb_sh, PCI_BRIDGE_BUS_REG);
153 pbus = PCI_BRIDGE_BUS_NUM_PRIMARY(reg);
154 sbus = PCI_BRIDGE_BUS_NUM_SECONDARY(reg);
155
156 /*
157 * XXX We don't know how to map interrupts on the Primary
158 * XXX PCI bus right now.
159 */
160 if (pa->pa_bus == pbus) {
161 printf("iq80310_pci_intr_map: can't map interrupts on "
162 "Primary bus\n");
163 return (1);
164 }
165
166 tag = pci_make_tag(pa->pa_pc, sbus, 7, 0);
167
168 /* Make sure the PPB is there. */
169 reg = pci_conf_read(pa->pa_pc, tag, PCI_ID_REG);
170 if (PCI_VENDOR(reg) == PCI_VENDOR_INVALID ||
171 PCI_VENDOR(reg) == 0) {
172 /*
173 * That's odd... no PPB there? Oh well, issue a warning
174 * and continue on.
175 */
176 printf("iq80310_pci_intr_map: PPB not found at %d/%d/%d ??\n",
177 sbus, 7, 0);
178 goto pinmap;
179 }
180
181 /* Make sure the device that's there is a PPB. */
182 reg = pci_conf_read(pa->pa_pc, tag, PCI_CLASS_REG);
183 if (PCI_CLASS(reg) != PCI_CLASS_BRIDGE ||
184 PCI_SUBCLASS(reg) != PCI_SUBCLASS_BRIDGE_PCI) {
185 /*
186 * That's odd... the device that's there isn't a PPB.
187 * Oh well, issue a warning and continue on.
188 */
189 printf("iq80310_pci_intr_map: %d/%d/%d isn't a PPB ??\n",
190 sbus, 7, 0);
191 goto pinmap;
192 }
193
194 /* Now read the PPB's secondary bus number. */
195 reg = pci_conf_read(pa->pa_pc, tag, PCI_BRIDGE_BUS_REG);
196 sbus = PCI_BRIDGE_BUS_NUM_SECONDARY(reg);
197
198 if (pa->pa_bus == sbus && pa->pa_device == 0 &&
199 pa->pa_function == 0) {
200 /* On-board i82559 Ethernet! */
201 *ihp = XINT3_IRQ(XINT3_ETHERNET);
202 return (0);
203 }
204
205 pinmap:
206 if (pa->pa_intrpin == 0) {
207 /* No IRQ used. */
208 return (1);
209 }
210 if (pa->pa_intrpin > 4) {
211 printf("iq80310_pci_intr_map: bad interrupt pin %d\n",
212 pa->pa_intrpin);
213 return (1);
214 }
215
216 /* INTD# is always in XINT3. */
217 if (pa->pa_intrpin == 4) {
218 *ihp = XINT3_IRQ(XINT3_SINTD);
219 return (0);
220 }
221
222 /* On pre-F boards, ALL of them are on XINT3. */
223 if (/*pre-F*/0)
224 *ihp = XINT3_IRQ(XINT3_SINTD);
225 else
226 *ihp = XINT0_IRQ(pa->pa_intrpin - 1);
227
228 return (0);
229 }
230 #endif /* list of IQ80310-based designs */
231
232 const char *
iq80310_pci_intr_string(void * v,pci_intr_handle_t ih,char * buf,size_t len)233 iq80310_pci_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len)
234 {
235 snprintf(buf, len, "iq80310 irq %" PRIu64, ih);
236 return buf;
237 }
238
239 const struct evcnt *
iq80310_pci_intr_evcnt(void * v,pci_intr_handle_t ih)240 iq80310_pci_intr_evcnt(void *v, pci_intr_handle_t ih)
241 {
242
243 /* XXX For now. */
244 return (NULL);
245 }
246
247 void *
iq80310_pci_intr_establish(void * v,pci_intr_handle_t ih,int ipl,int (* func)(void *),void * arg,const char * xname)248 iq80310_pci_intr_establish(void *v, pci_intr_handle_t ih, int ipl,
249 int (*func)(void *), void *arg, const char *xname)
250 {
251
252 return (iq80310_intr_establish(ih, ipl, func, arg));
253 }
254
255 void
iq80310_pci_intr_disestablish(void * v,void * cookie)256 iq80310_pci_intr_disestablish(void *v, void *cookie)
257 {
258
259 iq80310_intr_disestablish(cookie);
260 }
261