1 /* $NetBSD: intel_rc6.c,v 1.3 2021/12/19 11:49:11 riastradh Exp $ */
2
3 /*
4 * SPDX-License-Identifier: MIT
5 *
6 * Copyright © 2019 Intel Corporation
7 */
8
9 #include <sys/cdefs.h>
10 __KERNEL_RCSID(0, "$NetBSD: intel_rc6.c,v 1.3 2021/12/19 11:49:11 riastradh Exp $");
11
12 #include <linux/pm_runtime.h>
13
14 #include "i915_drv.h"
15 #include "intel_gt.h"
16 #include "intel_gt_pm.h"
17 #include "intel_rc6.h"
18 #include "intel_sideband.h"
19
20 /**
21 * DOC: RC6
22 *
23 * RC6 is a special power stage which allows the GPU to enter an very
24 * low-voltage mode when idle, using down to 0V while at this stage. This
25 * stage is entered automatically when the GPU is idle when RC6 support is
26 * enabled, and as soon as new workload arises GPU wakes up automatically as
27 * well.
28 *
29 * There are different RC6 modes available in Intel GPU, which differentiate
30 * among each other with the latency required to enter and leave RC6 and
31 * voltage consumed by the GPU in different states.
32 *
33 * The combination of the following flags define which states GPU is allowed
34 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
35 * RC6pp is deepest RC6. Their support by hardware varies according to the
36 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
37 * which brings the most power savings; deeper states save more power, but
38 * require higher latency to switch to and wake up.
39 */
40
rc6_to_gt(struct intel_rc6 * rc6)41 static struct intel_gt *rc6_to_gt(struct intel_rc6 *rc6)
42 {
43 return container_of(rc6, struct intel_gt, rc6);
44 }
45
rc6_to_uncore(struct intel_rc6 * rc)46 static struct intel_uncore *rc6_to_uncore(struct intel_rc6 *rc)
47 {
48 return rc6_to_gt(rc)->uncore;
49 }
50
rc6_to_i915(struct intel_rc6 * rc)51 static struct drm_i915_private *rc6_to_i915(struct intel_rc6 *rc)
52 {
53 return rc6_to_gt(rc)->i915;
54 }
55
set(struct intel_uncore * uncore,i915_reg_t reg,u32 val)56 static inline void set(struct intel_uncore *uncore, i915_reg_t reg, u32 val)
57 {
58 intel_uncore_write_fw(uncore, reg, val);
59 }
60
gen11_rc6_enable(struct intel_rc6 * rc6)61 static void gen11_rc6_enable(struct intel_rc6 *rc6)
62 {
63 struct intel_uncore *uncore = rc6_to_uncore(rc6);
64 struct intel_engine_cs *engine;
65 enum intel_engine_id id;
66
67 /* 2b: Program RC6 thresholds.*/
68 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
69 set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
70
71 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
72 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
73 for_each_engine(engine, rc6_to_gt(rc6), id)
74 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
75
76 set(uncore, GUC_MAX_IDLE_COUNT, 0xA);
77
78 set(uncore, GEN6_RC_SLEEP, 0);
79
80 set(uncore, GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
81
82 /*
83 * 2c: Program Coarse Power Gating Policies.
84 *
85 * Bspec's guidance is to use 25us (really 25 * 1280ns) here. What we
86 * use instead is a more conservative estimate for the maximum time
87 * it takes us to service a CS interrupt and submit a new ELSP - that
88 * is the time which the GPU is idle waiting for the CPU to select the
89 * next request to execute. If the idle hysteresis is less than that
90 * interrupt service latency, the hardware will automatically gate
91 * the power well and we will then incur the wake up cost on top of
92 * the service latency. A similar guide from plane_state is that we
93 * do not want the enable hysteresis to less than the wakeup latency.
94 *
95 * igt/gem_exec_nop/sequential provides a rough estimate for the
96 * service latency, and puts it under 10us for Icelake, similar to
97 * Broadwell+, To be conservative, we want to factor in a context
98 * switch on top (due to ksoftirqd).
99 */
100 set(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 60);
101 set(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 60);
102
103 /* 3a: Enable RC6 */
104 rc6->ctl_enable =
105 GEN6_RC_CTL_HW_ENABLE |
106 GEN6_RC_CTL_RC6_ENABLE |
107 GEN6_RC_CTL_EI_MODE(1);
108
109 set(uncore, GEN9_PG_ENABLE,
110 GEN9_RENDER_PG_ENABLE |
111 GEN9_MEDIA_PG_ENABLE |
112 GEN11_MEDIA_SAMPLER_PG_ENABLE);
113 }
114
gen9_rc6_enable(struct intel_rc6 * rc6)115 static void gen9_rc6_enable(struct intel_rc6 *rc6)
116 {
117 struct intel_uncore *uncore = rc6_to_uncore(rc6);
118 struct intel_engine_cs *engine;
119 enum intel_engine_id id;
120 u32 rc6_mode;
121
122 /* 2b: Program RC6 thresholds.*/
123 if (INTEL_GEN(rc6_to_i915(rc6)) >= 10) {
124 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
125 set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
126 } else if (IS_SKYLAKE(rc6_to_i915(rc6))) {
127 /*
128 * WaRsDoubleRc6WrlWithCoarsePowerGating:skl Doubling WRL only
129 * when CPG is enabled
130 */
131 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
132 } else {
133 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
134 }
135
136 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
137 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
138 for_each_engine(engine, rc6_to_gt(rc6), id)
139 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
140
141 set(uncore, GUC_MAX_IDLE_COUNT, 0xA);
142
143 set(uncore, GEN6_RC_SLEEP, 0);
144
145 /*
146 * 2c: Program Coarse Power Gating Policies.
147 *
148 * Bspec's guidance is to use 25us (really 25 * 1280ns) here. What we
149 * use instead is a more conservative estimate for the maximum time
150 * it takes us to service a CS interrupt and submit a new ELSP - that
151 * is the time which the GPU is idle waiting for the CPU to select the
152 * next request to execute. If the idle hysteresis is less than that
153 * interrupt service latency, the hardware will automatically gate
154 * the power well and we will then incur the wake up cost on top of
155 * the service latency. A similar guide from plane_state is that we
156 * do not want the enable hysteresis to less than the wakeup latency.
157 *
158 * igt/gem_exec_nop/sequential provides a rough estimate for the
159 * service latency, and puts it around 10us for Broadwell (and other
160 * big core) and around 40us for Broxton (and other low power cores).
161 * [Note that for legacy ringbuffer submission, this is less than 1us!]
162 * However, the wakeup latency on Broxton is closer to 100us. To be
163 * conservative, we have to factor in a context switch on top (due
164 * to ksoftirqd).
165 */
166 set(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 250);
167 set(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 250);
168
169 /* 3a: Enable RC6 */
170 set(uncore, GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
171
172 /* WaRsUseTimeoutMode:cnl (pre-prod) */
173 if (IS_CNL_REVID(rc6_to_i915(rc6), CNL_REVID_A0, CNL_REVID_C0))
174 rc6_mode = GEN7_RC_CTL_TO_MODE;
175 else
176 rc6_mode = GEN6_RC_CTL_EI_MODE(1);
177
178 rc6->ctl_enable =
179 GEN6_RC_CTL_HW_ENABLE |
180 GEN6_RC_CTL_RC6_ENABLE |
181 rc6_mode;
182
183 /*
184 * WaRsDisableCoarsePowerGating:skl,cnl
185 * - Render/Media PG need to be disabled with RC6.
186 */
187 if (!NEEDS_WaRsDisableCoarsePowerGating(rc6_to_i915(rc6)))
188 set(uncore, GEN9_PG_ENABLE,
189 GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE);
190 }
191
gen8_rc6_enable(struct intel_rc6 * rc6)192 static void gen8_rc6_enable(struct intel_rc6 *rc6)
193 {
194 struct intel_uncore *uncore = rc6_to_uncore(rc6);
195 struct intel_engine_cs *engine;
196 enum intel_engine_id id;
197
198 /* 2b: Program RC6 thresholds.*/
199 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
200 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
201 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
202 for_each_engine(engine, rc6_to_gt(rc6), id)
203 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
204 set(uncore, GEN6_RC_SLEEP, 0);
205 set(uncore, GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
206
207 /* 3: Enable RC6 */
208 rc6->ctl_enable =
209 GEN6_RC_CTL_HW_ENABLE |
210 GEN7_RC_CTL_TO_MODE |
211 GEN6_RC_CTL_RC6_ENABLE;
212 }
213
gen6_rc6_enable(struct intel_rc6 * rc6)214 static void gen6_rc6_enable(struct intel_rc6 *rc6)
215 {
216 struct intel_uncore *uncore = rc6_to_uncore(rc6);
217 struct drm_i915_private *i915 = rc6_to_i915(rc6);
218 struct intel_engine_cs *engine;
219 enum intel_engine_id id;
220 u32 rc6vids, rc6_mask;
221 int ret;
222
223 set(uncore, GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
224 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
225 set(uncore, GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
226 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
227 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
228
229 for_each_engine(engine, rc6_to_gt(rc6), id)
230 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
231
232 set(uncore, GEN6_RC_SLEEP, 0);
233 set(uncore, GEN6_RC1e_THRESHOLD, 1000);
234 if (IS_IVYBRIDGE(i915))
235 set(uncore, GEN6_RC6_THRESHOLD, 125000);
236 else
237 set(uncore, GEN6_RC6_THRESHOLD, 50000);
238 set(uncore, GEN6_RC6p_THRESHOLD, 150000);
239 set(uncore, GEN6_RC6pp_THRESHOLD, 64000); /* unused */
240
241 /* We don't use those on Haswell */
242 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
243 if (HAS_RC6p(i915))
244 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
245 if (HAS_RC6pp(i915))
246 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
247 rc6->ctl_enable =
248 rc6_mask |
249 GEN6_RC_CTL_EI_MODE(1) |
250 GEN6_RC_CTL_HW_ENABLE;
251
252 rc6vids = 0;
253 ret = sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS,
254 &rc6vids, NULL);
255 if (IS_GEN(i915, 6) && ret) {
256 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
257 } else if (IS_GEN(i915, 6) &&
258 (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
259 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
260 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
261 rc6vids &= 0xffff00;
262 rc6vids |= GEN6_ENCODE_RC6_VID(450);
263 ret = sandybridge_pcode_write(i915, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
264 if (ret)
265 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
266 }
267 }
268
269 /* Check that the pcbr address is not empty. */
chv_rc6_init(struct intel_rc6 * rc6)270 static int chv_rc6_init(struct intel_rc6 *rc6)
271 {
272 struct intel_uncore *uncore = rc6_to_uncore(rc6);
273 resource_size_t pctx_paddr, paddr;
274 resource_size_t pctx_size = 32 * SZ_1K;
275 u32 pcbr;
276
277 pcbr = intel_uncore_read(uncore, VLV_PCBR);
278 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
279 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
280 paddr = rc6_to_i915(rc6)->dsm.end + 1 - pctx_size;
281 GEM_BUG_ON(paddr > U32_MAX);
282
283 pctx_paddr = (paddr & ~4095);
284 intel_uncore_write(uncore, VLV_PCBR, pctx_paddr);
285 }
286
287 return 0;
288 }
289
vlv_rc6_init(struct intel_rc6 * rc6)290 static int vlv_rc6_init(struct intel_rc6 *rc6)
291 {
292 struct drm_i915_private *i915 = rc6_to_i915(rc6);
293 struct intel_uncore *uncore = rc6_to_uncore(rc6);
294 struct drm_i915_gem_object *pctx;
295 resource_size_t pctx_paddr;
296 resource_size_t pctx_size = 24 * SZ_1K;
297 u32 pcbr;
298
299 pcbr = intel_uncore_read(uncore, VLV_PCBR);
300 if (pcbr) {
301 /* BIOS set it up already, grab the pre-alloc'd space */
302 resource_size_t pcbr_offset;
303
304 pcbr_offset = (pcbr & ~4095) - i915->dsm.start;
305 pctx = i915_gem_object_create_stolen_for_preallocated(i915,
306 pcbr_offset,
307 I915_GTT_OFFSET_NONE,
308 pctx_size);
309 if (IS_ERR(pctx))
310 return PTR_ERR(pctx);
311
312 goto out;
313 }
314
315 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
316
317 /*
318 * From the Gunit register HAS:
319 * The Gfx driver is expected to program this register and ensure
320 * proper allocation within Gfx stolen memory. For example, this
321 * register should be programmed such than the PCBR range does not
322 * overlap with other ranges, such as the frame buffer, protected
323 * memory, or any other relevant ranges.
324 */
325 pctx = i915_gem_object_create_stolen(i915, pctx_size);
326 if (IS_ERR(pctx)) {
327 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
328 return PTR_ERR(pctx);
329 }
330
331 GEM_BUG_ON(range_overflows_t(u64,
332 i915->dsm.start,
333 pctx->stolen->start,
334 U32_MAX));
335 pctx_paddr = i915->dsm.start + pctx->stolen->start;
336 intel_uncore_write(uncore, VLV_PCBR, pctx_paddr);
337
338 out:
339 rc6->pctx = pctx;
340 return 0;
341 }
342
chv_rc6_enable(struct intel_rc6 * rc6)343 static void chv_rc6_enable(struct intel_rc6 *rc6)
344 {
345 struct intel_uncore *uncore = rc6_to_uncore(rc6);
346 struct intel_engine_cs *engine;
347 enum intel_engine_id id;
348
349 /* 2a: Program RC6 thresholds.*/
350 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
351 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
352 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
353
354 for_each_engine(engine, rc6_to_gt(rc6), id)
355 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
356 set(uncore, GEN6_RC_SLEEP, 0);
357
358 /* TO threshold set to 500 us (0x186 * 1.28 us) */
359 set(uncore, GEN6_RC6_THRESHOLD, 0x186);
360
361 /* Allows RC6 residency counter to work */
362 set(uncore, VLV_COUNTER_CONTROL,
363 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
364 VLV_MEDIA_RC6_COUNT_EN |
365 VLV_RENDER_RC6_COUNT_EN));
366
367 /* 3: Enable RC6 */
368 rc6->ctl_enable = GEN7_RC_CTL_TO_MODE;
369 }
370
vlv_rc6_enable(struct intel_rc6 * rc6)371 static void vlv_rc6_enable(struct intel_rc6 *rc6)
372 {
373 struct intel_uncore *uncore = rc6_to_uncore(rc6);
374 struct intel_engine_cs *engine;
375 enum intel_engine_id id;
376
377 set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
378 set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
379 set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
380
381 for_each_engine(engine, rc6_to_gt(rc6), id)
382 set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
383
384 set(uncore, GEN6_RC6_THRESHOLD, 0x557);
385
386 /* Allows RC6 residency counter to work */
387 set(uncore, VLV_COUNTER_CONTROL,
388 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
389 VLV_MEDIA_RC0_COUNT_EN |
390 VLV_RENDER_RC0_COUNT_EN |
391 VLV_MEDIA_RC6_COUNT_EN |
392 VLV_RENDER_RC6_COUNT_EN));
393
394 rc6->ctl_enable =
395 GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
396 }
397
bxt_check_bios_rc6_setup(struct intel_rc6 * rc6)398 static bool bxt_check_bios_rc6_setup(struct intel_rc6 *rc6)
399 {
400 struct intel_uncore *uncore = rc6_to_uncore(rc6);
401 struct drm_i915_private *i915 = rc6_to_i915(rc6);
402 u32 rc6_ctx_base, rc_ctl, rc_sw_target;
403 bool enable_rc6 = true;
404
405 rc_ctl = intel_uncore_read(uncore, GEN6_RC_CONTROL);
406 rc_sw_target = intel_uncore_read(uncore, GEN6_RC_STATE);
407 rc_sw_target &= RC_SW_TARGET_STATE_MASK;
408 rc_sw_target >>= RC_SW_TARGET_STATE_SHIFT;
409 DRM_DEBUG_DRIVER("BIOS enabled RC states: "
410 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
411 onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
412 onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
413 rc_sw_target);
414
415 if (!(intel_uncore_read(uncore, RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
416 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
417 enable_rc6 = false;
418 }
419
420 /*
421 * The exact context size is not known for BXT, so assume a page size
422 * for this check.
423 */
424 rc6_ctx_base =
425 intel_uncore_read(uncore, RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
426 if (!(rc6_ctx_base >= i915->dsm_reserved.start &&
427 rc6_ctx_base + PAGE_SIZE < i915->dsm_reserved.end)) {
428 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
429 enable_rc6 = false;
430 }
431
432 if (!((intel_uncore_read(uncore, PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1 &&
433 (intel_uncore_read(uncore, PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1 &&
434 (intel_uncore_read(uncore, PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1 &&
435 (intel_uncore_read(uncore, PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1)) {
436 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
437 enable_rc6 = false;
438 }
439
440 if (!intel_uncore_read(uncore, GEN8_PUSHBUS_CONTROL) ||
441 !intel_uncore_read(uncore, GEN8_PUSHBUS_ENABLE) ||
442 !intel_uncore_read(uncore, GEN8_PUSHBUS_SHIFT)) {
443 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
444 enable_rc6 = false;
445 }
446
447 if (!intel_uncore_read(uncore, GEN6_GFXPAUSE)) {
448 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
449 enable_rc6 = false;
450 }
451
452 if (!intel_uncore_read(uncore, GEN8_MISC_CTRL0)) {
453 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
454 enable_rc6 = false;
455 }
456
457 return enable_rc6;
458 }
459
rc6_supported(struct intel_rc6 * rc6)460 static bool rc6_supported(struct intel_rc6 *rc6)
461 {
462 struct drm_i915_private *i915 = rc6_to_i915(rc6);
463
464 if (!HAS_RC6(i915))
465 return false;
466
467 if (intel_vgpu_active(i915))
468 return false;
469
470 if (is_mock_gt(rc6_to_gt(rc6)))
471 return false;
472
473 if (IS_GEN9_LP(i915) && !bxt_check_bios_rc6_setup(rc6)) {
474 dev_notice(i915->drm.dev,
475 "RC6 and powersaving disabled by BIOS\n");
476 return false;
477 }
478
479 return true;
480 }
481
rpm_get(struct intel_rc6 * rc6)482 static void rpm_get(struct intel_rc6 *rc6)
483 {
484 GEM_BUG_ON(rc6->wakeref);
485 pm_runtime_get_sync(pci_dev_dev(rc6_to_i915(rc6)->drm.pdev));
486 rc6->wakeref = true;
487 }
488
rpm_put(struct intel_rc6 * rc6)489 static void rpm_put(struct intel_rc6 *rc6)
490 {
491 GEM_BUG_ON(!rc6->wakeref);
492 pm_runtime_put(pci_dev_dev(rc6_to_i915(rc6)->drm.pdev));
493 rc6->wakeref = false;
494 }
495
pctx_corrupted(struct intel_rc6 * rc6)496 static bool pctx_corrupted(struct intel_rc6 *rc6)
497 {
498 struct drm_i915_private *i915 = rc6_to_i915(rc6);
499
500 if (!NEEDS_RC6_CTX_CORRUPTION_WA(i915))
501 return false;
502
503 if (intel_uncore_read(rc6_to_uncore(rc6), GEN8_RC6_CTX_INFO))
504 return false;
505
506 dev_notice(i915->drm.dev,
507 "RC6 context corruption, disabling runtime power management\n");
508 return true;
509 }
510
__intel_rc6_disable(struct intel_rc6 * rc6)511 static void __intel_rc6_disable(struct intel_rc6 *rc6)
512 {
513 struct drm_i915_private *i915 = rc6_to_i915(rc6);
514 struct intel_uncore *uncore = rc6_to_uncore(rc6);
515
516 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
517 if (INTEL_GEN(i915) >= 9)
518 set(uncore, GEN9_PG_ENABLE, 0);
519 set(uncore, GEN6_RC_CONTROL, 0);
520 set(uncore, GEN6_RC_STATE, 0);
521 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
522 }
523
intel_rc6_init(struct intel_rc6 * rc6)524 void intel_rc6_init(struct intel_rc6 *rc6)
525 {
526 struct drm_i915_private *i915 = rc6_to_i915(rc6);
527 int err;
528
529 /* Disable runtime-pm until we can save the GPU state with rc6 pctx */
530 rpm_get(rc6);
531
532 if (!rc6_supported(rc6))
533 return;
534
535 if (IS_CHERRYVIEW(i915))
536 err = chv_rc6_init(rc6);
537 else if (IS_VALLEYVIEW(i915))
538 err = vlv_rc6_init(rc6);
539 else
540 err = 0;
541
542 /* Sanitize rc6, ensure it is disabled before we are ready. */
543 __intel_rc6_disable(rc6);
544
545 rc6->supported = err == 0;
546 }
547
intel_rc6_sanitize(struct intel_rc6 * rc6)548 void intel_rc6_sanitize(struct intel_rc6 *rc6)
549 {
550 if (rc6->enabled) { /* unbalanced suspend/resume */
551 rpm_get(rc6);
552 rc6->enabled = false;
553 }
554
555 if (rc6->supported)
556 __intel_rc6_disable(rc6);
557 }
558
intel_rc6_enable(struct intel_rc6 * rc6)559 void intel_rc6_enable(struct intel_rc6 *rc6)
560 {
561 struct drm_i915_private *i915 = rc6_to_i915(rc6);
562 struct intel_uncore *uncore = rc6_to_uncore(rc6);
563
564 if (!rc6->supported)
565 return;
566
567 GEM_BUG_ON(rc6->enabled);
568
569 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
570
571 if (IS_CHERRYVIEW(i915))
572 chv_rc6_enable(rc6);
573 else if (IS_VALLEYVIEW(i915))
574 vlv_rc6_enable(rc6);
575 else if (INTEL_GEN(i915) >= 11)
576 gen11_rc6_enable(rc6);
577 else if (INTEL_GEN(i915) >= 9)
578 gen9_rc6_enable(rc6);
579 else if (IS_BROADWELL(i915))
580 gen8_rc6_enable(rc6);
581 else if (INTEL_GEN(i915) >= 6)
582 gen6_rc6_enable(rc6);
583
584 rc6->manual = rc6->ctl_enable & GEN6_RC_CTL_RC6_ENABLE;
585 if (NEEDS_RC6_CTX_CORRUPTION_WA(i915))
586 rc6->ctl_enable = 0;
587
588 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
589
590 if (unlikely(pctx_corrupted(rc6)))
591 return;
592
593 /* rc6 is ready, runtime-pm is go! */
594 rpm_put(rc6);
595 rc6->enabled = true;
596 }
597
intel_rc6_unpark(struct intel_rc6 * rc6)598 void intel_rc6_unpark(struct intel_rc6 *rc6)
599 {
600 struct intel_uncore *uncore = rc6_to_uncore(rc6);
601
602 if (!rc6->enabled)
603 return;
604
605 /* Restore HW timers for automatic RC6 entry while busy */
606 set(uncore, GEN6_RC_CONTROL, rc6->ctl_enable);
607 }
608
intel_rc6_park(struct intel_rc6 * rc6)609 void intel_rc6_park(struct intel_rc6 *rc6)
610 {
611 struct intel_uncore *uncore = rc6_to_uncore(rc6);
612
613 if (!rc6->enabled)
614 return;
615
616 if (unlikely(pctx_corrupted(rc6))) {
617 intel_rc6_disable(rc6);
618 return;
619 }
620
621 if (!rc6->manual)
622 return;
623
624 /* Turn off the HW timers and go directly to rc6 */
625 set(uncore, GEN6_RC_CONTROL, GEN6_RC_CTL_RC6_ENABLE);
626 set(uncore, GEN6_RC_STATE, 0x4 << RC_SW_TARGET_STATE_SHIFT);
627 }
628
intel_rc6_disable(struct intel_rc6 * rc6)629 void intel_rc6_disable(struct intel_rc6 *rc6)
630 {
631 if (!rc6->enabled)
632 return;
633
634 rpm_get(rc6);
635 rc6->enabled = false;
636
637 __intel_rc6_disable(rc6);
638 }
639
intel_rc6_fini(struct intel_rc6 * rc6)640 void intel_rc6_fini(struct intel_rc6 *rc6)
641 {
642 struct drm_i915_gem_object *pctx;
643
644 intel_rc6_disable(rc6);
645
646 pctx = fetch_and_zero(&rc6->pctx);
647 if (pctx)
648 i915_gem_object_put(pctx);
649
650 if (rc6->wakeref)
651 rpm_put(rc6);
652 }
653
vlv_residency_raw(struct intel_uncore * uncore,const i915_reg_t reg)654 static u64 vlv_residency_raw(struct intel_uncore *uncore, const i915_reg_t reg)
655 {
656 u32 lower, upper, tmp;
657 int loop = 2;
658
659 /*
660 * The register accessed do not need forcewake. We borrow
661 * uncore lock to prevent concurrent access to range reg.
662 */
663 lockdep_assert_held(&uncore->lock);
664
665 /*
666 * vlv and chv residency counters are 40 bits in width.
667 * With a control bit, we can choose between upper or lower
668 * 32bit window into this counter.
669 *
670 * Although we always use the counter in high-range mode elsewhere,
671 * userspace may attempt to read the value before rc6 is initialised,
672 * before we have set the default VLV_COUNTER_CONTROL value. So always
673 * set the high bit to be safe.
674 */
675 set(uncore, VLV_COUNTER_CONTROL,
676 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
677 upper = intel_uncore_read_fw(uncore, reg);
678 do {
679 tmp = upper;
680
681 set(uncore, VLV_COUNTER_CONTROL,
682 _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH));
683 lower = intel_uncore_read_fw(uncore, reg);
684
685 set(uncore, VLV_COUNTER_CONTROL,
686 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
687 upper = intel_uncore_read_fw(uncore, reg);
688 } while (upper != tmp && --loop);
689
690 /*
691 * Everywhere else we always use VLV_COUNTER_CONTROL with the
692 * VLV_COUNT_RANGE_HIGH bit set - so it is safe to leave it set
693 * now.
694 */
695
696 return lower | (u64)upper << 8;
697 }
698
intel_rc6_residency_ns(struct intel_rc6 * rc6,const i915_reg_t reg)699 u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, const i915_reg_t reg)
700 {
701 struct drm_i915_private *i915 = rc6_to_i915(rc6);
702 struct intel_uncore *uncore = rc6_to_uncore(rc6);
703 u64 time_hw, prev_hw, overflow_hw;
704 unsigned int fw_domains;
705 unsigned long flags;
706 unsigned int i;
707 u32 mul, div;
708
709 if (!rc6->supported)
710 return 0;
711
712 /*
713 * Store previous hw counter values for counter wrap-around handling.
714 *
715 * There are only four interesting registers and they live next to each
716 * other so we can use the relative address, compared to the smallest
717 * one as the index into driver storage.
718 */
719 i = (i915_mmio_reg_offset(reg) -
720 i915_mmio_reg_offset(GEN6_GT_GFX_RC6_LOCKED)) / sizeof(u32);
721 if (WARN_ON_ONCE(i >= ARRAY_SIZE(rc6->cur_residency)))
722 return 0;
723
724 fw_domains = intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ);
725
726 spin_lock_irqsave(&uncore->lock, flags);
727 intel_uncore_forcewake_get__locked(uncore, fw_domains);
728
729 /* On VLV and CHV, residency time is in CZ units rather than 1.28us */
730 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
731 mul = 1000000;
732 div = i915->czclk_freq;
733 overflow_hw = BIT_ULL(40);
734 time_hw = vlv_residency_raw(uncore, reg);
735 } else {
736 /* 833.33ns units on Gen9LP, 1.28us elsewhere. */
737 if (IS_GEN9_LP(i915)) {
738 mul = 10000;
739 div = 12;
740 } else {
741 mul = 1280;
742 div = 1;
743 }
744
745 overflow_hw = BIT_ULL(32);
746 time_hw = intel_uncore_read_fw(uncore, reg);
747 }
748
749 /*
750 * Counter wrap handling.
751 *
752 * But relying on a sufficient frequency of queries otherwise counters
753 * can still wrap.
754 */
755 prev_hw = rc6->prev_hw_residency[i];
756 rc6->prev_hw_residency[i] = time_hw;
757
758 /* RC6 delta from last sample. */
759 if (time_hw >= prev_hw)
760 time_hw -= prev_hw;
761 else
762 time_hw += overflow_hw - prev_hw;
763
764 /* Add delta to RC6 extended raw driver copy. */
765 time_hw += rc6->cur_residency[i];
766 rc6->cur_residency[i] = time_hw;
767
768 intel_uncore_forcewake_put__locked(uncore, fw_domains);
769 spin_unlock_irqrestore(&uncore->lock, flags);
770
771 return mul_u64_u32_div(time_hw, mul, div);
772 }
773
intel_rc6_residency_us(struct intel_rc6 * rc6,i915_reg_t reg)774 u64 intel_rc6_residency_us(struct intel_rc6 *rc6, i915_reg_t reg)
775 {
776 return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(rc6, reg), 1000);
777 }
778
779 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
780 #include "selftest_rc6.c"
781 #endif
782