1 /* $NetBSD: intel_lrc.h,v 1.2 2021/12/18 23:45:30 riastradh Exp $ */ 2 3 /* 4 * Copyright © 2014 Intel Corporation 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 */ 25 26 #ifndef _INTEL_LRC_H_ 27 #define _INTEL_LRC_H_ 28 29 #include <linux/types.h> 30 31 struct drm_printer; 32 33 struct drm_i915_private; 34 struct i915_gem_context; 35 struct i915_request; 36 struct intel_context; 37 struct intel_engine_cs; 38 39 /* Execlists regs */ 40 #define RING_ELSP(base) _MMIO((base) + 0x230) 41 #define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234) 42 #define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4) 43 #define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244) 44 #define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH (1 << 3) 45 #define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT (1 << 0) 46 #define CTX_CTRL_RS_CTX_ENABLE (1 << 1) 47 #define CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT (1 << 2) 48 #define GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE (1 << 8) 49 #define RING_CONTEXT_STATUS_PTR(base) _MMIO((base) + 0x3a0) 50 #define RING_EXECLIST_SQ_CONTENTS(base) _MMIO((base) + 0x510) 51 #define RING_EXECLIST_CONTROL(base) _MMIO((base) + 0x550) 52 53 #define EL_CTRL_LOAD (1 << 0) 54 55 /* The docs specify that the write pointer wraps around after 5h, "After status 56 * is written out to the last available status QW at offset 5h, this pointer 57 * wraps to 0." 58 * 59 * Therefore, one must infer than even though there are 3 bits available, 6 and 60 * 7 appear to be * reserved. 61 */ 62 #define GEN8_CSB_ENTRIES 6 63 #define GEN8_CSB_PTR_MASK 0x7 64 #define GEN8_CSB_READ_PTR_MASK (GEN8_CSB_PTR_MASK << 8) 65 #define GEN8_CSB_WRITE_PTR_MASK (GEN8_CSB_PTR_MASK << 0) 66 67 #define GEN11_CSB_ENTRIES 12 68 #define GEN11_CSB_PTR_MASK 0xf 69 #define GEN11_CSB_READ_PTR_MASK (GEN11_CSB_PTR_MASK << 8) 70 #define GEN11_CSB_WRITE_PTR_MASK (GEN11_CSB_PTR_MASK << 0) 71 72 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */ 73 #define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */ 74 #define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */ 75 /* in Gen12 ID 0x7FF is reserved to indicate idle */ 76 #define GEN12_MAX_CONTEXT_HW_ID (GEN11_MAX_CONTEXT_HW_ID - 1) 77 78 enum { 79 INTEL_CONTEXT_SCHEDULE_IN = 0, 80 INTEL_CONTEXT_SCHEDULE_OUT, 81 INTEL_CONTEXT_SCHEDULE_PREEMPTED, 82 }; 83 84 /* Logical Rings */ 85 void intel_logical_ring_cleanup(struct intel_engine_cs *engine); 86 87 int intel_execlists_submission_setup(struct intel_engine_cs *engine); 88 89 /* Logical Ring Contexts */ 90 /* At the start of the context image is its per-process HWS page */ 91 #define LRC_PPHWSP_PN (0) 92 #define LRC_PPHWSP_SZ (1) 93 /* After the PPHWSP we have the logical state for the context */ 94 #define LRC_STATE_PN (LRC_PPHWSP_PN + LRC_PPHWSP_SZ) 95 96 /* Space within PPHWSP reserved to be used as scratch */ 97 #define LRC_PPHWSP_SCRATCH 0x34 98 #define LRC_PPHWSP_SCRATCH_ADDR (LRC_PPHWSP_SCRATCH * sizeof(u32)) 99 100 void intel_execlists_set_default_submission(struct intel_engine_cs *engine); 101 102 void intel_lr_context_reset(struct intel_engine_cs *engine, 103 struct intel_context *ce, 104 u32 head, 105 bool scrub); 106 107 void intel_execlists_show_requests(struct intel_engine_cs *engine, 108 struct drm_printer *m, 109 void (*show_request)(struct drm_printer *m, 110 struct i915_request *rq, 111 const char *prefix), 112 unsigned int max); 113 114 struct intel_context * 115 intel_execlists_create_virtual(struct intel_engine_cs **siblings, 116 unsigned int count); 117 118 struct intel_context * 119 intel_execlists_clone_virtual(struct intel_engine_cs *src); 120 121 int intel_virtual_engine_attach_bond(struct intel_engine_cs *engine, 122 const struct intel_engine_cs *master, 123 const struct intel_engine_cs *sibling); 124 125 struct intel_engine_cs * 126 intel_virtual_engine_get_sibling(struct intel_engine_cs *engine, 127 unsigned int sibling); 128 129 bool 130 intel_engine_in_execlists_submission_mode(const struct intel_engine_cs *engine); 131 132 #endif /* _INTEL_LRC_H_ */ 133